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PDF PR31500ABC Data sheet ( Hoja de datos )
| Número de pieza | PR31500ABC | |
| Descripción | Poseidon embedded processor | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
MIPS
PR31500
Poseidon embedded processor
Preliminary specification
Version 0.1
1996 Sep 24
Philips
Semiconductors
1 page  
Philips Semiconductors
Poseidon embedded processor
Preliminary specification
MIPS
PR31500
IR Module
• IR consumer mode
– allows control of consumer electronic devices such as stereos,
TVs, VCRs, etc.
– programmable pulse parameters
– external analog LED circuitry
• IRDA communication mode
– allows communication with other IRDA devices such as FAX
machines, copiers, printers, etc.
– supported by UART module within PR31500
– external analog receiver preamp and LED circuitry
– data rate = up to 115 Kbps at 1 meter
• IR FSK communication mode
– supported by UART module within PR31500
– external analog IR chip(s) perform frequency modulation to
generate the desired IR communication mode protocol
– data rate = up to 36000 bps at 3 meters
• carrier detect state machine
– periodically enables IR receiver to check if a valid carrier is
present
Power Module
• power-down modes for individual internal peripheral modules
• serial (SPI port) power supply control interface supported
• power management state machine has 4 states: RUNNING,
DOZING, SLEEP, and COMA
Serial Interconnect Bus (SIB) Module
• PR31500 contains holding and shift registers to support the serial
interface to the UCB1100 and/or other optional codec devices
• interface compatible with slave mode 3 of Crystal CS4216 codec
• synchronous, frame-based protocol
• PR31500 always master source of clock and frame frequency and
phase; programmable clock frequency
• each SIB frame consists of 128 clock cycles, further divided into 2
subframes or words of 64 bits each (supports up to 2 devices
simultaneously)
• independent DMA support for audio receive and transmit, telecom
receive and transmit
• supports 8-bit or 16-bit mono telecom formats
• supports 8-bit or 16-bit mono or stereo audio formats
• independently programmable audio and telecom sample rates
• CPU read/write registers for subframe control and status
System Peripheral Interface (SPI) Module
• provides interface to SPI peripherals and devices
• full-duplex, synchronous serial data transfers (data in, data out,
and clock signals)
• PR31500 supplies dedicated chip select and interrupt for an SPI
interface serial power supply
• 8-bit or 16-bit data word lengths for the SPI interface
• programmable SPI baud rate
Timer Module
• Real Time Clock (RTC) and Timer
• 40-bit counter (30.517 µsec granularity);
maximum uninterrupted time = 388.36 days
• 40-bit alarm register (30.517 µsec granularity)
• 16-bit periodic timer (0.868 µsec granularity);
maximum timeout = 56.8 msec
• interrupts on alarm, timer, and prior to RTC roll-over
UART Module
• 2 independent full-duplex UARTs
• programmable baud rate generator
• UART-A port used for serial control interface to external IR
module
• UART-B port used for general purpose serial control interface
• UART-A and UART-B DMA support for receive and transmit
Video Module
• bit-mapped graphics
• supports monochrome, grey scale, or color modes
• time-based dithering algorithm for grey scale and color modes
• supports multiple screen sizes
• supports split and non-split displays
• variable size and relocatable video buffer
• DMA support for fetching image data from video buffer
Little/Big Endian Configuration
The PR31500 can be configures as a Big Endian or as a Little
Endian processor based on the /LB endian pin at power-up.
The byte ordering is as follows:
LITTLE ENDIAN
D[31:24]
D[23:16]
D[15:8]
D[7:0]
/CAS3
/CAS2
/CAS1
/CAS0
BIG ENDIAN
D[7:0]
D[15:8]
D[23:16]
D[31:24]
/CAS0
/CAS1
/CAS2
/CAS3
1996 Sep 24
5
5 Page 
Philips Semiconductors
Poseidon embedded processor
Preliminary specification
MIPS
PR31500
PIN #
NAME
UART and IR Pins
55 TXD
54 RXD
59 IROUT
58 IRIN
RXPWR
62 CARDET
Video Pins
91 FRAME
93 DF
94 LOAD
95 CP
101, 100, VDAT(3:0)
99, 98
90 DISPON
Test Pins
74 TESTSIU
71 TESTCPU
72 TESTIN
73 VIDDONE
Spare Pins
NC4–1
34
32, 31
Power Supply Pins
VDD (34 each)
VSS (34 each)
TYPE
NAME AND FUNCTION
O This pin is the UART transmit signal from the UARTA module.
I This pin is the UART receive signal to the UARTA module.
O This pin is the UART transmit signal from the UARTB module or the Consumer IR output signal if
Consumer IR mode is enabled.
I This pin is the UART receive signal to the UARTB module.
O This pin is the receiver power output control signal to the external communication IR analog
circuitry.
I This pin is the carrier detect input signal from the external communication IR analog circuitry.
O This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is
used by the LCD to return it’s pointers to the top of the display. The Video Module asserts FRAME
after all the lines of the LCD have been shifted and transferred, producing a full frame of display.
O This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected
to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column
voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every
frame or can be configured to toggle every programmable number of LOAD signals.
O This pin is the line synchronization pulse signal between the Video Module and the LCD, and is
used by the LCD to transfer the contents of it’s horizontal line shift register to the LCD panel for
display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted
into the LCD.
O This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of
CP and sampled by the LCD on the falling edge of CP.
O These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit
non-split displays. For 4-bit split and 8-bit non-split displays, an external register is required to
demultiplex the 4-bit data into the desired 8 parallel data lines needed for the LCD.
O This pin is the display-on enable signal for the LCD.
I This pin allows external logic to initiate read or write transactions to PR31500 registers. The
TESTSIU mode is enabled by toggling this signal after the device has powered up. Once the
function is enabled, if the TESTSIU pin is high when the bus is arbitrated (using /DREQ and
/DGRNT), then external logic can initiate read and write transactions to PR31500 registers. This
pin is used for debugging purposes only.
I This pin allows numerous internal CPU core signals to be brought to external PR31500 pins, in
place of the normal signals assigned to these pins. The CPU core signals assigned to their
respective pins during TESTCPU mode are vendor-dependent. The TESTCPU mode is enabled
by asserting this TESTCPU signal, and this function is provided for generating test vectors for the
CPU core. This pin is used for debugging purposes only.
I This pin is reserved for vendor-dependent use. This pin is used for debugging purposes only.
O This signal is used to synchronize UCB1100 to read touchscreen input, when there is no video
data shifted into LCD panel.
No
Connect
–
–
These pins are reserved for future use and should be left unconnected.
Reserved.
Reserved.
+3.3V
GND
These pins are the power pins for PR31500 and should be connected to the digital +3.3V power
supply VSTANDBY.
These pins are the ground pins for PR31500 and should be connected to digital ground.
NOTE: For some vendor-dependent implementations of PR31500, pin 131 may be used for a filter
capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground).
1996 Sep 24
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PR31500ABC.PDF ] | |
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