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부품번호 1345 기능
기능 1345-Type Receiver with Clock Recovery and Data Retiming
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1345 데이터시트, 핀배열, 회로
Data Sheet
January 2000
1345-Type Receiver with
Clock Recovery and Data Retiming
Applications
s Telecommunications:
— Inter- and intraoffice SONET/ITU-T SDH
— Subscriber loop
— Metropolitan area networks
s High-speed data communications
Operating at 1.3 µm or 1.55 µm wavelengths and at
155 Mbits/s or 622 Mbits/s, the versatile 1345-Type Receiver is
manufactured in a 20-pin, plastic DIP with a multimode fiber
pigtail.
Features
s Backward compatible with 1330 family
s Space-saving, self-contained, 20-pin plastic DIP
s Silicon based ICs
s Single 5 V power supply operation including
photocurrent monitor capability
s Exceeds all SONET (GR-253-CORE) and ITU-T
G.958 jitter requirements
s Clocked decision circuit
s Regenerated differential clock signal
s Wide dynamic range
s Qualified to meet the intent of Telcordia Technolo-
gies ™ reliability practices
s Operates at data rates of 155 Mbits/s or
622 Mbits/s
s Positive ECL (PECL) data outputs
s CMOS (TTL) link-status flag output
s Operation at 1.3 µm or 1.55 µm wavelengths
s Operating temperature range of –40 °C to +85 °C
Description
The 1345-Type fiber-optic receiver is designed for
use in transmission systems or medium- to high-
speed data communication applications. Used in
intermediate- and long-reach applications, the
receiver operates at the SONET OC-3 or OC-12 data
rate as well as the ITU-T synchronous digital hierar-
chy (SDH) rate of STM-1 or STM-4, depending on
the receiver model chosen. The receiver meets all
present Telcordia Technologies GR-253-CORE
requirements, the current ANSI T1X1.5 intraoffice
specifications, and the ITU-T G.957 and G.958 rec-
ommendations. Compact packaging, a high level of
integration, and a wide dynamic range make these
receivers ideal for data communications.
Manufactured in a 20-pin DIP, the receiver consists of
a planar InGaAs PIN photodetector, a silicon pream-
plifier, a silicon bipolar limiting amplifier that converts
the small signal to ECL levels, a timing recovery unit
to recover the clock, and a silicon bipolar decision cir-
cuit.




1345 pdf, 반도체, 판매, 대치품
1345-Type Receiver with
Clock Recovery and Data Retiming
Data Sheet
January 2000
Application Information
Data and Flag Outputs
The 1345 receiver is a highly sensitive fiber-optic
receiver. Although the data outputs are digital logic lev-
els (PECL), the device should be thought of as an ana-
log component. When laying out the printed-wiring
board (PWB), the 1345 receiver should be given the
same type of consideration one would give to a sensi-
tive analog component.
At a minimum, a double-sided printed-wiring board with
a large component-side ground plane beneath the
receiver must be used. In applications that include
many other high-speed devices, a multilayer PWB is
highly recommended. This permits the placement of
power and ground connections on separate layers,
which helps minimize the coupling of unwanted signal
noise into the power supplies of the receiver.
Layout Considerations
A fiber-optic receiver employs a very high-gain, wide-
bandwidth transimpedance amplifier. The amplifier
detects and amplifies signals that are only tens of nA in
amplitude. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's loss of signal (FLAG) circuit. To
minimize the coupling of unwanted noise into the
receiver, route high-level, high-speed signals such as
transmitter inputs and clock lines as far away as possi-
ble from the receiver pins. If this is not possible, then
the PWB layout engineer should consider interleaving
the receiver signal and flag traces with ground traces in
order to provide the required isolation.
Noise that couples into the receiver through the power
supply pins can also degrade device performance. The
application schematics, Figures 2—3, show recom-
mended power supply filtering that helps minimize
noise coupling into the receiver. The bypass capacitors
should be high-quality ceramic devices rated for RF
applications. They should be surface-mount compo-
nents placed as close as possible to the receiver power
supply pins. The ferrite bead should have as high an
impedance as possible in the frequency range that is
most likely to cause problems. This will vary for each
application and is dependent on the signaling frequen-
cies present on the application circuit card. Surface-
mount, high-impedance beads are available from sev-
eral manufacturers.
4
The data and clock outputs of the 1345 receiver are
driven by open-emitter NPN transistors which have an
output impedance of approximately 7 . Each output
can provide approximately 50 mA maximum output cur-
rent. Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (DATA and DATA) and clock outputs
(CLOCK and CLOCK) should be terminated identically.
The signal lines connecting the data and clock outputs
to the next device should be equal in length and should
have matched impedances.
Controlled impedance stripline or microstrip construc-
tion must be used in order not to degrade the quality of
the signal into the next component and to minimize
reflections back into the receiver. Excessive ringing due
to reflections caused by improperly terminated signal
lines makes it difficult for the component receiving
these signals to decipher the proper logic levels and
may cause transitions to occur where none were
intended. Also, by minimizing high frequency ringing
due to reflections caused by improperly designed and
terminated signal lines, possible EMI problems can be
avoided. The applications sections in the Signetics™
ECL 10K/100K Data Manual or the National Semicon-
ductor ® ECL Logic Databook and Design Guide pro-
vide excellent design information on ECL interfacing.
The FLAG and FLAG outputs of the OC-3/STM-1
155 Mbits/s receiver and the OC-12/STM-4 622 Mbits/s
receiver are 5 V TTL logic-level compatible. The FLAG
output is provided directly by the comparator IC. How-
ever, the FLAG output is derived from the FLAG output
through an inverter. Excessive loading of the FLAG out-
put can cause the FLAG output to malfunction.
Recommended User Interface
The 1345 receiver is designed to be operated from a
5 V power supply and provides raised or pseudo-ECL
(PECL) data outputs. Figures 2 and 3 show two possi-
ble application circuits for the 1345 receiver. Figure 2
represents an application for a PECL compatible inter-
face while Figure 3 shows a possible application for an
ac-coupled, ECL-compatible interface. In both
instances, the DATA outputs are terminated with a
Thévenin equivalent circuit, which provides the equiva-
lent of a 50 load terminated to (VCC – 2 V). A single
50 resistor terminated to (VCC – 2 V) could also be
used, but this requires a second power supply. Other
methods of terminating ECL-type outputs are dis-
cussed in the references previously mentioned.
Agere Systems Inc.

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1345 전자부품, 판매, 대치품
Data Sheet
January 2000
1345-Type Receiver with
Clock Recovery and Data Retiming
Characteristics (continued)
Table 2. Optical Characteristics
Parameter
Symbol
Data Rates
Mbits/s
Min
Typ
Max*
Unit
Measured Average Sensitivity:*, †
OC-3
OC-12
Maximum Input Power
Link Status Flag Threshold:
Decreasing Light Input
Decreasing Light Input
Flag Hysteresis
Flag Response Time
Detector Responsivity
PRL
PRL
PMAX
OC-3/STM-1
OC-12/STM-4
OC-3/STM-1
OC-12/STM-4
LSTD
LSTI
HYS
tFLAG
R
OC-3/STM-1
OC-12/STM-4
OC-3/STM-1
OC-12/STM-4
155/622
155/622
155/622
0
–6
–50
–50
–50
–50
0.5
3
0.7
38
–32.5
2
–4
–41
–38.8
–38
–35
3
0.8
–36
–30
–37.5
–32.5
–37.0
–32.0
6
100
1.2
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
µs
A/W
* For a 1 x 10–10 BER. Measured with a 223 – 1 pseudorandom word optical input having a 50% average duty cycle.
† Whenever the flag output is deasserted (logic low), the DATA and CLOCK outputs are silenced. See the Flag Output section on
page 2 for the DATA and CLOCK output signal levels.
‡ Power supply noise in excess of 50 mVp-p may degrade the performance of the receiver. See User Interface section for recom-
mended power supply filtering.
DATAOUT
50%
CLOCKOUT
50%
TCDA
Figure 4. Clock/Data Alignment
1-725(C)
Agere Systems Inc.
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