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PDF PSD835F2V-C-12MI Data sheet ( Hoja de datos )
| Número de pieza | PSD835F2V-C-12MI | |
| Descripción | Configurable Memory System on a Chip for 8-Bit Microcontrollers | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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PSD835G2
Configurable Memory System on a Chip
for 8-Bit Microcontrollers
PRELIMINARY DATA
FEATURES SUMMARY
s 5 V±10% Single Supply Voltage:
s Up to 4 Mbit of Primary Flash Memory (8
uniform sectors)
s 256Kbit Secondary Flash Memory (4 uniform
sectors)
s Up to 64 Kbit SRAM
s Over 3,000 Gates of PLD: DPLD and CPLD
s 52 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD
Figure 1. Packages
TQFP80 (U)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/3
1 page  
CNTL0,
CNTL1,
CNTL2
PROG.
MCU BUS
INTRF.
AD0 – AD15
ADIO
PORT
PF0 – PF7
PROG.
PORT
PORT
F
PG0 – PG7
PROG.
PORT
PORT
G
CLKIN
ADDRESS/DATA/CONTROL BUS
PLD
INPUT
BUS
PAGE
REGISTER
EMBEDDED
ALGORITHM
4 MBIT MAIN FLASH
MEMORY
8 SECTORS
SECTOR
FLASH DECODE
PLD (DPLD)
SELECTS
82 SECTOR
SELECTS
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
SRAM SELECT
64 KBIT BATTERY
BACKUP SRAM
PERIP I/O MODE SELECTS
CSIOP
RUNTIME CONTROL
AND I/O REGISTERS
82 FLASH ISP CPLD
(CPLD)
8 EXT CS to PORT C or F
16 OUTPUT MICRO⇔CELLS
PORT A & B
CLKIN
24 INPUT MICRO⇔CELLS
PORT A ,B & C
MICRO⇔CELL FEEDBACK OR PORT INPUT
CLKIN
PORT F
GLOBAL
CONFIG. &
SECURITY
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
*Additional address lines can be brought into PSD via Port A, B, C, D, or F.
POWER
MANGMT
UNIT
VSTDBY
(PE6)
PROG.
PORT PA0 – PA7
PORT
A
PROG.
PORT
PORT
B
PB0 – PB7
PROG.
PORT
PORT
C
PC0 – PC7
PROG.
PORT
PORT
D
PD0 – PD3
PROG.
PORT
PORT
E
PE0 – PE7
5 Page 
PSD8XX Family
Table 5.
PSD835G2
Pin
Descriptions
(cont.)
PSD835G2
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
PE3 74 I/O Port E, PE3. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain 2. Latched address output.
3. TDO output for JTAG/ISP interface.
PE4 75 I/O Port E, PE4. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain 2. Latched address output.
3. TSTAT output for the ISP interface.
4. Rdy/Bsy — for in-circuit Parallel Programming.
PE5 76 I/O Port E, PE5. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain 2. Latched address output.
3. TERR active low output for ISP interface.
PE6 77 I/O Port E, PE6. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain 2. Latched address output.
3. Vstby — SRAM standby voltage input for battery
backup SRAM
PE7 78 I/O Port E, PE7. This port is pin configurable and has multiple
CMOS functions:
or Open 1. MCU I/O — standard output or input port.
Drain 2. Latched address output.
3. Vbaton — battery backup indicator output. Goes high when
power is drawn from an external battery.
PF0-PF7
31-38 I/O
CMOS
or Open
Drain
Port F, PF0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Input to the PLD.
3. Latched address outputs.
4. As address A0-3 inputs in 80C51XA mode
5. As data bus port (D0-7) in non-multiplexed bus configuration
PG0-PG7 21-28 I/O
CMOS
or Open
Drain
Port G, PG0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address outputs.
GND
8,30,
49,50,
70
VCC
9,29,
69
10
11 Page | ||
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| PDF Descargar | [ Datasheet PSD835F2V-C-12MI.PDF ] | |
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