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부품번호 PSD835F2V-C-90B81 기능
기능 Configurable Memory System on a Chip for 8-Bit Microcontrollers
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PSD835F2V-C-90B81 데이터시트, 핀배열, 회로
PSD835G2
Configurable Memory System on a Chip
for 8-Bit Microcontrollers
PRELIMINARY DATA
FEATURES SUMMARY
s 5 V±10% Single Supply Voltage:
s Up to 4 Mbit of Primary Flash Memory (8
uniform sectors)
s 256Kbit Secondary Flash Memory (4 uniform
sectors)
s Up to 64 Kbit SRAM
s Over 3,000 Gates of PLD: DPLD and CPLD
s 52 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD
Figure 1. Packages
TQFP80 (U)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/3




PSD835F2V-C-90B81 pdf, 반도체, 판매, 대치품
PSD835G2
2.0
Key Features
PSD8XX Family
t A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80188, 80C251
Motorola 68HC11 and 68HC16
Philips 8031 and 80C51XA
Zilog Z80, Z8 and Z180
Infineon C500 family
t 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
t Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
t 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
t CPLD with 16 Output MicroCells (OMCs) and 24 Input MicroCells (IMCs). The
CPLD may be used to efficiently implement a variety of logic functions for internal
and external control. Examples include state machines, loadable shift registers, and
loadable counters. The CPLD can also generate eight external chip selects.
t Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
t 52 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
I/O ports may be configured as open-drain outputs.
t Standby current as low as 50 µA for 5 V devices.
t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
t Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
t Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD8XX into Power Down Mode.
t Erase/Write cycles:
Flash memory – 100,000 minimum
PLD – 1,000 minimum
3.0 PSD8XX
Series
Table 1. PSD8XX Product Matrix
Part #
PSD8XX
Series
Device
Flash
Flash
Main
Boot
Serial ISP Memory Memory
I/O PLD Input
Output PLD JTAG/ISP Kbit
Kbit SRAM
Pins Inputs Macrocells Macrocells Outputs Port 8 Sectors (4 Sectors) Kbit
PSD835G2 52
24
16
24 Yes
4096
256
64
PSD8XX PSD813F2
27 57
24
16
19 Yes
1024
256
16
PSD834F2
27 57
24
16
19 Yes
2048
256
64
PSD833F2
27 57
24
16
19 Yes
1024
256
64
Supply
Voltage
5V
5V
5V
5V
3

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PSD835F2V-C-90B81 전자부품, 판매, 대치품
PSD8XX Family
PSD8XX
Architectural
Overview
(cont.)
PSD835G2
4.5 ISP via JTAG Port
In-System Programming can be performed through the JTAG pins on Port E. This serial
interface allows complete programming of the entire PSD835G2 device. A blank device
can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO)
can be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin
assignments.
4.6 In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD835G2 (memory, logic, configuration)
device can be programmed or erased without the use of the microcontroller.
Table 3. JTAG Signals on Port E
Port E Pins
JTAG Signal
PE0 TMS
PE1 TCK
PE2 TDI
PE3 TDO
PE4 TSTAT
PE5 TERR
4.7 In-Application re-Programming (IAP)
The main Flash memory can also be programmed in-system by the microcontroller
executing the programming algorithms out of the secondary Flash memory, or SRAM.
Since this is a sizable separate block, the application can also continue to operate. The
secondary Flash boot memory can be programmed the same way by executing out of the
main Flash memory. Table 4 indicates which programming methods can program different
functional blocks of the PSD8XX.
Table 4. Methods of Programming Different Functional Blocks of the PSD835G2
Functional Block
JTAG-ISP
Device
Programmer
IAP
Main Flash memory
Flash Boot memory
PLD Array (DPLD and CPLD)
PSD Configuration
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
4.8 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces for IAP.
4.9 Power Management Unit
The Power Management Unit (PMU) in the PSD835G2 gives the user control of the
power consumption on selected functional blocks based on system requirements. The
PMU includes an Automatic Power Down unit (APD) that will turn off device functions due
to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce
power consumption.
The PSD835G2 also has some bits that are configured at run-time by the MCU to reduce
power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off
and the CPLD will latch its outputs and go to standby until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the CPLD to reduce power consumption. See section 9.5.
6

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PSD835F2V-C-90B81

Configurable Memory System on a Chip for 8-Bit Microcontrollers

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