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PDF N748961N Data sheet ( Hoja de datos )
| Número de pieza | N748961N | |
| Descripción | Octal latched bidirectional Futurebus transceivers 3-State open-collector | |
| Fabricantes | Philips | |
| Logotipo |  |
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Philips Semiconductors FAST Products
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
Product specification
74F8960/74F8961
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω
• High drive (100mA) open collector drivers
on B port
• Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE futurebus standards
• Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity
• Controlled output ramp and multiple GND
pins minimize ground bounce
• Glitch-free power up/down operation
DESCRIPTION
The 74F8960 and 74F8961 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 100 mV
threshold region and a 4ns glitch filter.
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident switching is employed, therefore BTL
propagation delays are short. Although the
voltage swing is much less for BTL, so is its
receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8960 and 74F8961 A ports have TTL
3–state drivers and TTL receivers with a latch
function. A separate High–level control input
(VX) is provided to limit the A side output
level to a given voltage level (such as 3.3V).
For 5.0V systems, VX is simply tied to VCC.
The 74F8961 is the non–inverting version of
74F8960.
TYPE
74F8960
74F8961
TYPICAL PROPAGATION DELAY
6.5ns
6.5ns
TYPICAL SUPPLY CURRENT( TOTAL)
80mA
80mA
ORDERING INFORMATION
DESCRIPTION
28–pin plastic DIP (300 mil)1
28–pin PLCC1
NOTE: Thermal mounting techiques are recommended.
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F8960N, N748961N
N74F8960A, N74F8961A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
A0 – A8
PNP latched inputs
3.5/0.117
B0 – B8
Data inputs with threshold circuitry
5.0/0.167
OEA
A output enable input (active high)
1.0/0.033
OEB0, OEB1
B output enable inputs (active low)
1.0/0.033
LE Latch enable input (active low)
1.0/0.033
A0 – A7
3–state outputs
150/40
B0 – B7
Open collector outputs
NOTES:
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
OC/166.7
LOAD VALUE
HIGH/LOW
70µA/70µA
100µA/100µA
20µA/20µA
20µA/20µA
20µA/20µA
3mA/24mA
OC/100mA
December 19, 1990
1
853-1120 01322
1 page  
Philips Semiconductors FAST Products
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
Product specification
74F8960/74F8961
FUNCTION TABLE FOR 74F8960
INPUTS
LATCH OUTPUTS
OPERATING MODE
An Bn* LE OEA OEB OEB
01
HX L
L
L
L
STATE
H
An Bn
Z L A 3–state, data from A to B
LXL
L
L
L
L Z H**
XXH
L
L
L
Qn Z Qn A 3–state, latched data to B
––L
H
L
L
(1) (1) (1) Feedback: A to B, B to A
– HH
H
L
L
H (2)
H Z(2) Preconditioned latch enabling data transfer from B to A
– LH
H
L
L
H (2)
L Z(2)
– –H
H
L
L
Qn Qn Qn Latch state to A and B
HX L
L
H
X
H ZZ
l XL
L
H
X
l Z Z B and A 3–state
XXH
L
H
X
Qn Z Z
–HL
H
H
X
H HZ
–LL
H
H
H
L L Z B 3–state, data from B to A
– HH
H
H
H
Qn H Z
– LH
H
H
H
Qn L Z
HX L
L
X
H
H ZZ
l XL
L
X
H
l Z Z B and A 3–state
XXH
L
X
H
Qn Z Z
–HL
H
X
H
H HZ
–LL
H
X
H
L L Z B 3–state, data from B to A
– HH
H
X
H
Qn H Z
– LH
H
X
H
Qn L Z
NOTES:
1. H = High–voltage level
2. L = Low–voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance (off) state
6. Qn = High or low voltage level one setup time prior to the low–to–high LE transition.
7. (1) = Condition will cause a feedback loop path: A to B and B to A.
8. (2) = The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high.
9. H**= Goes to level of pullup voltage.
10. B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
December 19, 1990
5
5 Page 
Philips Semiconductors FAST Products
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
Product specification
74F8960/74F8961
AC WAVEFORMS
An, Bn, OEBn
VM
tPLH
VM
tPHL
An, Bn, OEBn
VM
tPHL
VM
tPLH
An, Bn
VM
VM
Waveform 1. Propagation delay for data to output
An, Bn
VM VM
Waveform 2. Propagation delay for data to output
An VM VM
VM VM
th(L)
th(H)
ts(L)
ts(H)
LE
VM VM
tw(L)
VM
Waveform 3. Data setup and hold times and LE pulse width
OEA
VM
VM
OEA
VM
VM
tPZH
tPHZ
VOH -0.3V
An VM
0V
Waveform 4. 3–state output enable time to high level
and output disable time from high level
tPZL
tPLZ
An VM
VOL +0.3V
Waveform 5. 3-state output enable time to low level
and output disable time from low level
NOTES:
1. For all waveforms, VM = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST SWITCH
tPLZ, tPZL closed
All other open
PULSE
GENERATOR
VIN
VCC
VOUT
D.U.T.
RL
RT CL RL
Test circuit for 3–state outputs on A port
VCC
7.0V
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
tw
VM
10%
tTHL (tf )
VM
10%
tTLH (tr )
tTLH (tr )
90%
VM
tw
tTHL (tf )
90%
VM
Input pulse definition
90%
AMP (V)
Low V
AMP (V)
10%
Low V
PULSE
GENERATOR
VIN
VOUT
D.U.T.
RU
INPUT PULSE REQUIREMENTS
family
74F amplitude Low V VM rep. rate tw tTLH
tTHL
RT CD
A port
B port
3.0V
3.0V
0.0V 1.5V
1.0V 1.5V
1MHz
1MHz
Test circuit for outputs on B port
DEFINITIONS:
RL =
CL =
RU =
CD =
RT =
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to ZOUT of pulse generators.
500ns 2.5ns 2.5ns
500ns 4.0ns 4.0ns
December 19, 1990
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet N748961N.PDF ] | |
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