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PDF N80930AD4 Data sheet ( Hoja de datos )
| Número de pieza | N80930AD4 | |
| Descripción | UNIVERSAL SERIAL BUS MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
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ADVANCE INFORMATION
8x930Ax
UNIVERSAL SERIAL BUS
MICROCONTROLLER
s Complete Universal Serial Bus
Specification 1.0 Compatibility
— Supports Isochronous and
Non-isochronous Data
— Bidirectional Half-duplex Link
s On-chip USB Transceiver
s Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
— NRZI Encoding/Decoding and
Bit-stuffing
s USB Reset Interrupt
s Four Transmit FIFOs
— Three 16-byte FIFOs
— One Configurable FIFO (up to
1 Kbyte)
s Four Receive FIFOs
— Three 16-byte FIFOs
— One Configurable FIFO (up to
1 Kbyte)
s Automatic Transmit/Receive FIFO
Management
s Suspend/Resume Operation
s Three New USB Interrupt Vectors
— USB Function Interrupt
— Start of Frame
— Suspend/Resume
s Phase-locked Loop
— 12 Mbps or 1.5 Mbps Data Rate
s Low Clock Mode
s User-selectable Configurations
— External Wait State
— Address Range
— Page Mode
s Real-time Wait Function
s 256-Kbyte External Code/Data Memory
Space
s On-chip ROM Options
— 0, 8, or 16 Kbytes
s 1 Kbyte On-chip Data RAM
s Four Input/Output Ports
— 1 Open-drain port
— 3 Quasi-bidirectional Ports
s Programmable Counter Array (PCA)
— 5 Capture/Compare Modules
s Serial I/O Port (UART)
s Hardware Watchdog Timer
s Three Flexible 16-bit Timer/Counters
s Power-saving Idle and Powerdown
Modes
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Doublewords
s Code Compatible with MCS 51 and MCS
251 Microcontrollers
s 6 or 12 MHz Crystal Operation
The 8x930Ax USB microcontroller is based on an 8xC251Sx microcontroller core. It consists of standard
8xC251Sx peripherals plus an added USB function. The 8x930Ax uses the standard instruction set of the
MCS 251 architecture, which is binary code compatible with the MCS 51 architecture. The USB function
integrates the USB transceiver, serial bus interface engine (SIE), function interface unit (FIU) and
transmit/receive FIFOs. The USB function also supports full-speed/low-speed data rates, suspend/resume
modes, isochronous/non-isochronous transfers, and is fully compliant with the USB rev 1.0 specification.
COPYRIGHT © INTEL CORPORATION, 1997
February 1997
Order Number: 272917-003
1 page  
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
System Bus and I/O Ports
P0.7:0
P2.7:0
Port 0
Drivers
Port 2
Drivers
ROM
RAM
I/O Ports and
Peripheral Signals
P1.7:0
P3.7:0
Port 1
Drivers
Port 3
Drivers
Memory Data (16)
Memory Address (16)
Bus Interface
Code Bus (16)
Code Address (24)
Instruction Sequencer
SRC1 (8)
SRC2 (8)
ALU
Register
File
Data
Memory
Interface
Peripheral
Interface
Interrupt
Handler
Clock
&
Reset
DST (16)
Microcontroller Core
† For details, see the USB module block diagram.
Figure 1. 8x930Ax Internal Block Diagram
ADVANCE INFORMATION
Watchdog
Timer
Timer/
Counters
PCA
Serial I/O
USB†
USB Ports
A4340-01
1
5 Page 
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
3.0 SIGNALS
Table 5. Signal Descriptions
Signal
Name
Type
Description
Alternate Function
A17 O 18th Address Bit (A17). Output to memory as 18th exter- P1.7/CEX4/WCLK
nal address bit (A17) in extended bus applications, depend-
ing on the values of bits RD0 and RD1 in configuration byte
UCONFIG0. See also RD#, PSEN#.
A16
A15:8†
AD7:0†
O Address Line 16. See RD#.
RD#
O Address Lines. Upper address lines for the external bus. P2.7:0
I/O Address/Data Lines. Multiplexed lower address lines and P0.7:0
data lines for external memory.
ALE O Address Latch Enable (ALE). ALE signals the start of an PROG#
external bus cycle and indicates that valid address informa-
tion is available on lines A15:8 and AD7:0. An external latch
can use ALE to demultiplex the address from the
address/data bus.
AVCC
PWR Analog VCC. A separate VCC input for the phase-locked loop
circuitry.
CEX2:0
CEX3
CEX4
I/O Programmable Counter Array (PCA) Input/Output Pins. P1.5:3
These are input signals for the PCA capture mode and out- P1.6/WAIT#
put signals for the PCA compare mode and PCA PWM
P1.7/A17/WCLK
mode.
DM0 I/O Data Minus. USB minus data line interface.
—
DP0 I/O Data Plus. USB plus data line interface.
—
EA# I External Access. Directs program memory accesses to
on-chip or off-chip code memory. For EA# strapped to
ground, all program memory accesses are off-chip. For EA#
strapped to VCC, program accesses on-chip ROM if the
address is within the range of the on-chip ROM; otherwise,
the access is off-chip. The value of EA# is latched at reset.
For devices without on-chip ROM, EA# must be strapped to
ground.
ECAP
ECI
I External Capacitor. Must be connected to a 1 µF capacitor
(or larger) to ensure proper operation of the differential line
driver. The other lead of the capacitor must be connected to
VSS.
I PCA External Clock Input. External clock input to the 16- P1.2
bit PCA timer.
INT1:0#
I External Interrupts 0 and 1. These inputs set bits IE1:0 in P3.3:2
the TCON register. If bits IT1:0 in the TCON register are
set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If
bits INT1:0 are clear, bits IE1:0 are set by a low level on
INT1:0#.
P0.7:0
I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port. AD7:0
† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
ADVANCE INFORMATION
7
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