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기능 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
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N80C186EA20 데이터시트, 핀배열, 회로
80C186EA 80C188EA AND 80L186EA 80L188EA
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y 80C186 Upgrade for Power Critical Applications
Y Fully Static Operation
Y True CMOS Inputs and Outputs
Y Integrated Feature Set
Static 186 CPU Core
Power Save Idle and Powerdown
Modes
Clock Generator
2 Independent DMA Channels
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
System-Level Testing Support
(High Impedance Test Mode)
Y Speed Versions Available (5V)
25 MHz (80C186EA25 80C188EA25)
20 MHz (80C186EA20 80C188EA20)
13 MHz (80C186EA13 80C188EA13)
Y Speed Versions Available (3V)
13 MHz (80L186EA13 80L188EA13)
8 MHz (80L186EA8 80L188EA8)
Y Direct Addressing Capability to
1 Mbyte Memory and 64 Kbyte I O
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EA only)
Y Available in the Following Packages
68-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin EIAJ Quad Flat Pack (QFP)
80-Pin Shrink Quad Flat Pack (SQFP)
Y Available in Extended Temperature
Range (b40 C to a85 C)
The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the
features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown
Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor
272432 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272432-003
COPYRIGHT INTEL CORPORATION 1995
1




N80C186EA20 pdf, 반도체, 판매, 대치품
80C186EA 80C188EA 80L186EA 80L188EA
INTRODUCTION
Unless specifically noted all references to the
80C186EA apply to the 80C188EA 80L186EA and
80L188EA References to pins that differ between
the 80C186EA 80L186EA and the 80C188EA
80L188EA are given in parentheses The ‘‘L’’ in the
part number denotes low voltage operation Physi-
cally and functionally the ‘‘C’’ and ‘‘L’’ devices are
identical
The 80C186EA is the second product in a new gen-
eration of low-power high-integration microproces-
sors It enhances the existing 80C186XL family by
offering new features and operating modes The
80C186EA is object code compatible with the
80C186XL embedded processor
The 80L186EA is the 3V version of the 80C186EA
The 80L186EA is functionally identical to the
80C186EA embedded processor Current
80C186EA customers can easily upgrade their de-
signs to use the 80L186EA and benefit from the re-
duced power consumption inherent in 3V operation
The feature set of the 80C186EA 80L186EA meets
the needs of low-power space-critical applications
Low-power applications benefit from the static de-
sign of the CPU core and the integrated peripherals
as well as low voltage operation Minimum current
consumption is achieved by providing a Powerdown
Mode that halts operation of the device and freezes
the clock circuits Peripheral design enhancements
ensure that non-initialized peripherals consume little
current
Space-critical applications benefit from the inte-
gration of commonly used system peripherals Two
flexible DMA channels perform CPU-independent
data transfers A flexible chip select unit simplifies
memory and peripheral interfacing The interrupt unit
provides sources for up to 128 external interrupts
and will prioritize these interrupts with those generat-
ed from the on-chip peripherals Three general pur-
pose timer counters round out the feature set of the
80C186EA
Figure 1 shows a block diagram of the 80C186EA
80C188EA The Execution Unit (EU) is an enhanced
8086 CPU core that includes dedicated hardware to
speed up effective address calculations enhance
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions
string move instructions that operate at full bus
bandwidth ten new instructions and static opera-
tion The Bus Interface Unit (BIU) is the same as that
found on the original 80C186 family products An
independent internal bus is used to allow communi-
cation between the BIU and internal peripherals
80C186EA CORE ARCHITECTURE
Bus Interface Unit
The 80C186EA core incorporates a bus controller
that generates local bus control signals In addition
it employs a HOLD HLDA protocol to share the local
bus with other bus masters
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data off
the local bus during a read operation SRDY and
ARDY input pins are provided to extend a bus cycle
beyond the minimum four states (clocks)
The local bus controller also generates two control
signals (DEN and DT R) when interfacing to exter-
nal transceiver chips This capability allows the addi-
tion of transceivers for simple buffering of the mulit-
plexed address data bus
Clock Generator
The processor provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter and two low-power operating
modes
The oscillator circuit is designed to be used with ei-
ther a parallel resonant fundamental or third-over-
tone mode crystal network Alternatively the oscilla-
tor circuit may be driven from an external clock
source Figure 2 shows the various operating modes
of the oscillator circuit
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components All AC timings are referenced to
CLKOUT
The following parameters are recommended when
choosing a crystal
Temperature Range
Application Specific
ESR (Equivalent Series Resistance)
60X max
C0 (Shunt Capacitance of Crystal)
7 0 pF max
CL (Load Capacitance)
Drive Level
20 pF g 2 pF
2 mW max
4
4

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N80C186EA20 전자부품, 판매, 대치품
80C186EA 80C188EA 80L186EA 80L188EA
PCB
Offset
Function
20H Interrupt Vector
22H Specific EOI
24H Reserved
26H Reserved
28H Interrupt Mask
2AH
Priority Mask
2C In-Service
2E Interrupt Request
30 Interrupt Status
32 TMR0 Interrupt Control
34 DMA0 Interrupt Control
36 DMA1 Interrupt Control
38 TMR1 Interrupt Control
3A TMR2 Interrupt Control
3C Reserved
3E Reserved
Figure 4 80C186EA Slave Mode Peripheral
Control Block Registers
DMA Control Unit
The 80C186EA DMA Contol Unit provides two inde-
pendent high-speed DMA channels Data transfers
can occur between memory and I O space in any
combination memory to memory memory to I O
I O to I O or I O to memory Data can be trans-
ferred either in bytes or words Transfers may pro-
ceed to or from either even or odd addresses but
even-aligned word transfers proceed at a faster rate
Each data transfer consumes two bus cycles (a mini-
mum of eight clocks) one cycle to fetch data and
the other to store data The chip-select ready logic
may be programmed to point to the memory or I O
space subject to DMA transfers in order to provide
hardware chip select lines DMA cycles run at higher
priority than general processor execution cycles
Chip-Select Unit
The 80C186EA Chip-Select Unit integrates logic
which provides up to 13 programmable chip-selects
to access both memories and peripherals In addi-
tion each chip-select can be programmed to auto-
matically terminate a bus cycle independent of the
condition of the SRDY and ARDY input pins The
chip-select lines are available for all memory and
I O bus cycles whether they are generated by the
CPU the DMA unit or the Refresh Control Unit
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed A 9-bit
counter controls the number of clocks between re-
fresh requests
A 9-bit address generator is maintained by the RCU
with the address presented on the A9 1 address
lines during the refresh bus cycle Address bits
A19 13 are programmable to allow the refresh ad-
dress block to be located on any 8 Kbyte boundary
Power Management
The 80C186EA has three operational modes to con-
trol the power consumption of the device They are
Power Save Mode Idle Mode and Powerdown
Mode
Power Save Mode divides the processor clock by a
programmable value to take advantage of the fact
that current is linearly proportional to frequency An
unmasked interrupt NMI or reset will cause the
80C186EA to exit Power Save Mode
Idle Mode freezes the clocks of the Execution Unit
and the Bus Interface Unit at a logic zero state while
all peripherals operate normally
Powerdown Mode freezes all internal clocks at a
logic zero level and disables the crystal oscillator All
internal registers hold their values provided VCC is
maintained Current consumption is reduced to tran-
sistor leakage only
7
7

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N80C186EA20

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Intel Corporation
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