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기능 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
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N80C31BH 데이터시트, 핀배열, 회로
80C31BH 80C51BH 87C51
MCS 51
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Automotive
Y Extended Automotive Temperature
Range (b40 C to a125 C Ambient)
Y High Performance CHMOS Process
Y Power Control Modes
Y 4 Kbyte On-Chip ROM EPROM
Y 128 x 8-bit RAM
Y 32 Programmable I O Lines
Y Two 16-Bit Timer Counters
Y 5 Interrupt Sources
Y Quick-Pulse EPROM Programming
Y 2-Level Program Memory Lock EPROM
Y Boolean Processor
Y Programmable Serial Port
Y TTL- and CMOS-Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y IDLE and POWER DOWN Modes
Y ONCE Mode Facilitates System Testing
Y Available in 12 MHz and 16 MHz
Versions
Y Available in PLCC and DIP Packages
(See Packaging Specification Order 231369)
The MCS 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are
functionally compatible with the standard MCS 51 HMOS microcontroller products This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS This combina-
tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set
Like the MCS 51 HMOS microcontroller versions the MCS 51 CHMOS microcontroller products have the
following features 4 Kbytes of EPROM ROM (87C51 80C51BH respectively) 128 bytes of RAM 32 I O lines
two 16-bit timer counters a five-source two-level interrupt structure a full duplex serial port and on-chip
oscillator and clock circuitry In addition the MCS 51 CHMOS microcontroller products exhibit low operating
power along with two software selectable modes of reduced activity for further power reduction Idle and
Power Down
The Idle mode freezes the CPU while allowing the RAM timer counters serial port and interrupt system to
continue functioning The Power Down mode saves the RAM contents but freezes the oscillator causing all
other chip functions to be inoperative
The 87C51 is the EPROM version of the 80C51BH It contains 4 Kbytes of on-chip program memory that can
be electrically programmed and can be erased by exposure to ultraviolet light The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm by which the entire 4 Kbyte array can be programmed in about
12 seconds
NOTICE
This datasheet contains information on products in full production Specifications within this datasheet
are subject to change without notice Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
January 1995
Order Number 270419-007




N80C31BH pdf, 반도체, 판매, 대치품
AUTOMOTIVE 80C31BH 80C51BH 87C51
Diagrams are for pin reference only Package sizes are not to scale
Pin (PDIP)
EPROM only
Do not connect reserved pins
270419 – 3
Figure 3 Pin Connections
Pad (PLCC)
270419 – 4
PIN DESCRIPTION
VCC Supply voltage during normal Idle and Power
Down operations
VSS Circuit ground
VSS1 VSS1 (EPROM PLCC only) secondary
ground Provided to reduce ground bounce and im-
prove power supply bypassing
NOTE
This pin is not a substitute for the VSS pin (pin 22)
For ROM and ROMless pin 1 is reserved do not
connect
Port 0 Port 0 is an 8-bit open drain bidirectional I O
port As an output port each pin can sink 8 LS TTL
inputs Port 0 pins that have 1s written to them float
and in that state can be used as high-impedance
inputs
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory In this
application it uses strong internal pullups when emit-
ting 1s
Port 0 also receives the code bytes during EPROM
programming and outputs the code bytes during
program verification External pullups are required
during program verification
Port 1 Port 1 is an 8-bit bidirectional I O port with
internal pullups Port 1 pins that have 1s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 1
pins that are externally being pulled low will source
4
current (IIL on the datasheet) because of the inter-
nal pullups
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion
Port 2 Port 2 is an 8-bit bidirectional I O port with
internal pullups Port 2 pins that have 1s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 2
pins that are externally being pulled low will source
current (IIL on the data sheet) because of the inter-
nal pullups
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX DPTR) In this application it uses
strong internal pullups when emitting 1s
During accesses to external Data Memory that use
8-bit addresses (MOVX Ri) Port 2 emits the con-
tents of the P2 Special Function Register
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification
Port 3 Port 3 is an 8-bit bidirectional I O port with
internal pullups Port 3 pins that have 1s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally being pulled low will source
current (IIL on the datasheet) because of the pull-
ups

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N80C31BH 전자부품, 판매, 대치품
AUTOMOTIVE 80C31BH 80C51BH 87C51
PROGRAM MEMORY LOCK
(EPROM Only)
The 87C51 contains two program memory lock
schemes Encrypted Verify and Lock Bits
Encrypted Verify The 87C51 implements a 32-
byte EPROM array that can be programmed by the
customer and which can then be used to encrypt
the program code bytes during EPROM verification
The EPROM verification procedure is performed as
usual except that each code byte comes out logical-
ly X-NORed with one of the 32 key bytes The key
bytes are gone through in sequence Therefore to
read the ROM code one has to know the 32 key
bytes in their proper sequence
Lock Bits Also on the chip are two Lock Bits which
can be left unprogrammed (U) or can be pro-
grammed (P) to obtain the following additional fea-
tures
Bit 1 Bit 2
Additional Features
UU
none
P U  Externally fetched code can not
access internal Program Memory
 Further programming disabled
U P (Reserved for Future definition )
P P  Externally fetched code can not
access internal Program Memory
 Further programming disabled
 Program verification is disabled
When Lock Bit 1 is programmed the logic level at
the EA pin is sampled and latched during reset If
the device is powered up without a reset the latch
initializes to a random value and holds that value
until reset is activated It is necessary that the
latched value of EA be in agreement with the current
logic level at that pin in order for the device to func-
tion properly
ONCE MODE
The ONCE (‘‘on-circuit emulation’’) mode facilitates
testing and debugging of systems using the 87C51
without the 87C51 having to be removed from the
circuit The ONCE mode is invoked by
1 Pull ALE low while the device is in reset and
PSEN is high
2 Hold ALE low as RST is deactivated
While the device is in ONCE mode the Port 0 pins
go into a float state and the other port pins and ALE
and PSEN are weakly pulled high The oscillator cir-
cuit remains active While the 87C51 is in this mode
an emulator or test CPU can be used to drive the
circuit Normal operation is restored when a normal
reset is applied
7

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부품번호상세설명 및 기능제조사
N80C31BH

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Intel Corporation
Intel Corporation
N80C31BH

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Intel Corporation
Intel Corporation

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