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부품번호 NWK914CG 기능
기능 PHY/PMD High Speed Copper Media Transceiver
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NWK914CG 데이터시트, 핀배열, 회로
NWK914D
NWK914D
PHY/PMD High Speed Copper Media Transceiver
Preliminary Information
DS4829 - 1.1 December 1997
The NWK914D is a Physical Layer device designed for
use in 100BASE-TX applications. The NWK914D has
integrated the 100mb/s transceiver, clock and data recovery
and NRZI conversion circuitry. It is designed for use in cost
effective NIC adapter cards and 100BASE-TX repeater and
switch applications.
The device connects through a 5 bit symbol interface
directly with any MAC controller that includes the PCS layer,
resulting in a simple and cost effective solution. It will also
interface with a PCS device such as the NWK935 to form a
complete 100BASE-TX Physical Layer for connection to the
IEEE 802.3 standard MII interface.
FEATURES
s Compatible with IEEE-802.3 Standards
s Operates over 100 Meters of STP and Category 5
UTP cable
s Five Bit TTL Level Symbol Interface
s Integrated Clock and Data Recovery
s Supports Full-duplex Operation
s Integral 10 Mb/s Buffer for Dual 10 Mb/s & 100 Mb/s
Applications
s Adaptive Equalization
s 25MHz to 125MHz Transmit Clock Multiplier
s Programmable TX Output Current
s Base Line Wander Correction
TTLGND 1
N/C 2
N/C 3
RXC 4
SDT 5
RDLVCC 6
N/C 7
N/C 8
RXPLLGND 9
LFRB 10
LFRA 11
RXPLLV CC 12
RXVCC 13
39 TTLGND
38 TEST
37 TESTIP
36 N10/100
35 LBEN
34 TDLVCC
33 TXOE
32 TXPLLVCC
31 LFTA
30 LFTB
29 TXPLLGND
28 BGAPGND
27 SUBGND
GP52
Fig.1 Pin connections - top view
s Single +5V supply
s 52 Pin PQFP package
ORDERING INFORMATION
NWK914D/CG/GP1N
MAC or
Repeater
Controller
IC
MII
Interface
NWK935
100 PCS
Symbol
Interface
NWK914D
Isolation
Magnetics
RJ-45
Fig.2 Simplified system diagram
1




NWK914CG pdf, 반도체, 판매, 대치품
NWK914D
When N10/100 is held low the 10Mb/s driver is selected.
This 10Mb/s driver consists of a differential analog buffer
designed to take a fully cable conditioned 10Mb/s signal
from the filter output of existing 10BASE-T electronics. The
10BASE-T signal is input on pins 10TXIN and 10TXIP. The
output current of the buffer is determined by the same
external RREF resistor on pin TXREF as used for the 100Mb/
s driver.
The unselected driver is switched to a tristated power
save mode. A low voltage shutdown circuit turns off both TX
drivers when VCC voltage falls to a level below the specified
minimum.
When operating in single 100Mb/s applications a 1:1
turn ratio magnetics will be used and therefore to attain the
desired line driving current of 40mA out of the secondary a
TXO output drive of 40mA is required. Using the above
formula it will be found that 1.3is the nearest prefered
value to that required to give the 40mA.
In the case of dual 10Mb/s and 100Mb/s applications a
2:1 turn ratio magnetics is recommended. The use of 2:1
magnetics enables a greater efficiency to be gained from
the 10Mb/s driver by using a lower output current. At the
same time this lower current is also true of the 100Mb/s
output where now only a 20mA drive is required. An RREF
value of 2.6Kis used to set this current. Internal current
ratioing within the device will ensure that the correct drive
current is chosen depending upon whether the drives are in
10Mb/s or 100Mb/s mode as selected by pin N10/100.
The RREF value can be adjusted to compensate for
different magnetics and board layouts. The object is to
achieve an output level of 2V p-p measured at the RJ45
socket in compliance with 802.3.
When the TXOE pin is held low the TXdrivers are tri-
stated regardless of the mode selected by the N10/100 pin.
Receiver Section
Equalizer
The equalizer circuit is necessary to compensate for
signal degradation due to cable losses, however over-
equalization must be avoided to prevent excessive overshoots
resulting in errors during the reception of MLT-3 data. Three
operating modes are therefore provided.
These three operating modes are controlled by the state
of tristate input 'EQSEL' and are described below:-
1) Auto Equalization ('EQSEL' floating)
Fully automatic equalization is achieved through the
use of a feedback loop driven by a control signal derived
from the signal amplitude. This provides adaptive control
and prevents over-modulation of the signal when short
cable lengths are used.
2) Full Equalization ('EQSEL' low)
In this mode, full equalization is applied to the input
signal irrespective of amplitude.
3) No Equalization ('EQSEL high)
The equalization circuit is disabled completely during
this mode.
Base Line Wander Correction
MLT-3 codes have significant low frequency components
in their spectrum which are not transmitted through the
transformers that couple the line to the board. This results in
'Base Line Wander', which can significantly reduce the
noise immunity of the receiver.
The purpose ot the correction circuit is to restore these
low frequency components through the use of a feedback
arrangement. The circuit will also correct any DC offset that
may exist on the receive signal.
Signal Detector
A signal detect circuit is provided which continuously
monitors the amplitude of the input signal being received on
pins RXIP and RXIN. After the input signal reaches the
specified level which the equalizer can correctly equalize,
SDT is asserted high. Conversely if the signal level falls
below a limit for reliable operation then SDT will go low.
Comparators MLT-3 to NRZ Decoder
The equalized MLT-3 data is then passed to a set of
window comparators which are used to determine the signal
level. The comparator outputs are OR’ed together to
reconstitute the NRZI data.
PLL Clock Recovery
This function consists of a 125MHz PLL that is locked to
the incoming data stream. The PLL is first centred to the
transmit clock multiplier using an internal analog reference
signal. Once a valid input signal is present, the PLL will lock
to, and thus extract the clock from, the incoming data
stream. Pins LFRA and LFRB are provided to set the VCO
characteristics. The recommended loop filter components
are shown in Fig.6.
125MHz Shifter to Parallel Data
The 125Mb/s serial data stream with an accompanying
phase related 125MHz clock is output from the PLL.
This data stream is clocked into the serial to parallel
register using the 125MHz clock. This data is then latched
prior to being clocked out on pins RDAT0 to RDAT4. A
25MHz clock, derived from the 125MHz PLL by a divide by
5, is used to clock the parallel data and is output to pin RXC.
Loopback Logic
Pin ‘LBEN’ controls loopback operation. A low level on
this pin defines normal operation, a high level defines
loopback mode. In loopback mode, the transmit data is
internally routed to the receive circuitry, SDT is forced high
and the TXOP and TXON outputs are disabled.
Test Pins and No-Connects
Two pins are provided on the product to aid testing in
production. These pins TEST(38), and TESTIP(37) must be
left unconnected for normal operation in application circuits.
Additionally, there are four No-Connect pins (2,3,7,8)
which also mustt be left unconnected for normal operation.
4

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NWK914CG 전자부품, 판매, 대치품
NWK914D
PCS
or
MAC
(with
embedded
PCS)
Xtal Osc.
1K
R1
100pF
.033µF
C2
See Table 2 for
these resistor values
TxVcc
C1
LFTA
REFCLK
R2
R5
LFTB TXREF TXGND
TXOP
5 TDAT0-4
TXON
R6
0.1µF CT
C4
TXC NWK914D
15
RXC
RXIP
R7
R9 68
5 RDAT0-4
RXIN
R8
15
LFRA LFRB
C3
R3 .01µF
6.2K
1:1
M
A
G
N
E
T
I
C
S
RJ45
Fig.6 Simplified 100BASE-TX system block diagram showing NWK914D external components
REF.
VALUE TOL. FUNC.
NOTES
C1
100pF
20% loop fltr
C2 0.033µF 20% loop fltr
C3
.01µF
20% loop fltr
R1
R2
R3
R5,R6
R7,R8
R9
1K
1300
6.2K
50
15
68
1% loop fltr
1% tx ref 1:1 magnetics
1% loop fltr
1% xmit 1:1 magnetics
1% rcv pad
1% rcv pad
R2
R5,R6
2.6K
200
1%
1%
tx ref 2:1 magnetics
xmit 2:1 magnetics
CT on transformer connects directly to
TX VCC with C4 omitted
2:1 magnetics
Table 2: External components
EXTERNAL REQUIREMENTS
The NWK914D requires a number of external components
for the device to function correctly and these are shown in
the simplified 100BASE-TX application circuit in Fig.6 and
the component value information given in Table 2.
Note that the values of R2, R5 and R6 vary depending
upon application. When using 1:1 magnetics, use the values
shown in the middle of Table 2 with note "1:1 magnetics".
When using 2:1 magnetics use the values shown in the last
two lines of Table 2. Please refer to the Transmit Line Driver
section on pages 3-4 for more information on these values.
For more detailed Application information please contact
your local Sales Office.
GLOSSARY OF TERMS AND ABREVIATIONS
MAC Media Access Control
MLT-3 Multi Level Transmit -3 levels
NRZ Non Return To Zero
NRZI Non Return to Zero Inverse
PCS Physical Coding Sublayer
PHY PHYsical Layer
PLL Phase Locked Loop
PMD Physical Media Dependent
UTP Unshielded Twisted Pair
RX Receive
STP
Shielded Twisted Pair
TX Transmit
UTP Unshielded Twisted Pair
VCO Voltage Controlled Oscillator
NWK914B
NWK914S
Base Line Wander Correction
TXREF resistor with 1:1 magnetics
-
620
improved to 100m
680
Table 3: Differences between NWK914B, NWK914S and NWK914D
NWK914D
improved to 100m
1300
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NWK914CG

PHY/PMD High Speed Copper Media Transceiver

Mitel Networks
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