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기능 Field-Programmable Gate Arrays
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OR2C40A 데이터시트, 핀배열, 회로
Data Sheet
June 1999
ORCA® Series 2
Field-Programmable Gate Arrays
Features
s High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
s High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
s Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
s Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
s Eight 3-state buffers per PFU for on-chip bus structures
s Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
s Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
s Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
s Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
s Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
Table 1. ORCA Series 2 FPGAs
s Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
s Upward bit stream compatible with the ORCA ATT2Cxx/
ATT2Txx series of devices
s Pinout-compatible with new ORCA Series 3 FPGAs
s TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
s Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
s Built-in boundary scan (IEEE*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
s Multiple configuration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
s Full PCI bus compliance for all devices
s Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ORCA Foundry
Development System support (for back-end implementa-
tion)
s New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
Usable
Gates*
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
# LUTs Registers
400
576
784
1024
1296
1600
2304
3600
400
576
724
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.




OR2C40A pdf, 반도체, 판매, 대치품
ORCA Series 2 FPGAs
Data Sheet
June 1999
Description (continued)
The FPGA’s functionality is determined by internal configuration RAM. The FPGA’s internal initialization/configura-
tion circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of
several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM on the
circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuring
FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP).
PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 TMID PT10 PT11 PT12 PT13 PT14 PT15 PT16 PT17 PT18
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9
R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18
R2C1 R2C2 R2C3 R2C4 R2C5 R2C6 R2C7 R2C8 R2C9
R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17 R2C18
vIQ
R3C1 R3C2 R3C3 R3C4 R3C5 R3C6 R3C7 R3C8 R3C9
R3C10 R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17 R3C18
R4C1 R4C2 R4C3 R4C4 R4C5 R4C6 R4C7 R4C8 R4C9
R4C10 R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17 R4C18
R5C1 R5C2 R5C3 R5C4 R5C5 R5C6 R5C7 R5C8 R5C9
R5C10 R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17 R5C18
R6C1 R6C2 R6C3 R6C4 R6C5 R6C6 R6C7 R6C8 R6C9
R6C10 R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17 R6C18
R7C1 R7C2 R7C3 R7C4 R7C5 R7C6 R7C7 R7C8 R7C9
R7C10 R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17 R7C18
R8C1 R8C2 R8C3 R8C4 R8C5 R8C6 R8C7 R8C8 R8C9
R8C10 R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17 R8C18
R9C1 R9C2 R9C3 R9C4 R9C5 R9C6 R9C7 R9C8 R9C9
hIQ
R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9
R9C10 R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17 R9C18
R10C10 R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18
R11C1 R11C2 R11C3 R11C4 R11C5 R11C6 R11C7 R11C8 R11C9
R12C1 R12C2 R12C3 R12C4 R12C5 R12C6 R12C7 R12C8 R12C9
R13C1 R13C2 R13C3 R13C4 R13C5 R13C6 R13C7 R13C8 R13C9
R11C10 R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18
R12C10 R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18
R13C10 R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18
R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9
R14C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18
R15C1 R15C2 R15C3 R15C4 R15C5 R15C6 R15C7 R15C8 R15C9
R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18
R16C1 R16C2 R16C3 R16C4 R16C5 R16C6 R16C7 R16C8 R16C9
R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18
R17C1 R17C2 R17C3 R17C4 R17C5 R17C6 R17C7 R17C8 R17C9
R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18
R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9
R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 BMID PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18
Figure 1. Series 2 Array
5-6779(F)
4 Lucent Technologies Inc.

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OR2C40A 전자부품, 판매, 대치품
Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
Table 3 lists the basic operating modes of the LUT. The
operating mode affects the functionality of the PFU
input and output ports and internal PFU routing. For
example, in some operating modes, the WD[3:0] inputs
are direct data inputs to the PFU latches/FFs. In the
dual 16 x 2 memory mode, the same WD[3:0] inputs
are used as a 4-bit data input bus into LUT memory.
The PFU is used in a variety of modes, as illustrated in
Figures 4 through 11, and it is these specific modes
that are most relevant to PFU functionality.
PFU Control Inputs
The four control inputs to the PFU are clock (CK), local
set/reset (LSR), clock enable (CE), and C0. The CK,
CE, and LSR inputs control the operation of all four
latches in the PFU. An active-low global set/reset
(GSRN) signal is also available to the latches/FFs in
every PFU. Their operation is discussed briefly here,
and in more detail in the Latches/Flip-Flops section.
The polarity of the control inputs can be inverted.
The CK input is distributed to each PFU from a vertical
or horizontal net. The CE input inhibits the latches/FFs
from responding to data inputs. The CE input can be
disabled, always enabling the clock. Each latch/FF can
be independently programmed to be set or reset by the
LSR and the global set/reset (GSRN) signals. Each
PFU’s LSR input can be configured as synchronous or
asynchronous. The GSRN signal is always asynchro-
nous. The LSR signal applies to all four latches/FFs in
a PFU. The LSR input can be disabled (the default).
The asynchronous set/reset is dominant over clocked
inputs.
The C0 input is used as an input into the special PFU
gates for wide functions in combinatorial logic mode.
In the memory modes, this input is also used as the
write-port enable input. The C0 input can be disabled
(the default).
used as LUT inputs. The use of these ports changes
based on the PFU operating mode.
The functionality of the LUT is determined by its operat-
ing mode. The entries in Table 3 show the basic modes
of operation for combinatorial logic, ripple, and memory
functions in the LUT. Depending on the operating
mode, the LUT can be divided into sub-LUTs. The LUT
is comprised of two 32-bit half look-up tables, HLUTA
and HLUTB. Each half look-up table (HLUT) is com-
prised of two quarter look-up tables (QLUTs). HLUTA
consists of QLUT2 and QLUT3, while HLUTB consists
of QLUT0 and QLUT1. The outputs of QLUT0, QLUT1,
QLUT2, and QLUT3 are F0, F1, F2, and F3, respec-
tively.
Table 3. Look-Up Table Operating Modes
Mode
Function
F4A Two functions of four inputs, some inputs
shared (QLUT2/QLUT3)
F4B Two functions of four inputs, some inputs
shared (QLUT0/QLUT1)
F5A One function of five inputs (HLUTA)
F5B One function of five inputs (HLUTB)
R 4-bit ripple (LUT)
MA 16 x 2 asynchronous memory (HLUTA)
MB 16 x 2 asynchronous memory (HLUTB)
SSPM 16 x 4 synchronous single-port memory
SDPM 16 x 2 synchronous dual-port memory
For combinatorial logic, the LUT can be used to do any
single function of six inputs, any two functions of five
inputs, or four functions of four inputs (with some inputs
shared), and three special functions based on the two
five-input functions and C0.
Look-Up Table Operating Modes
The look-up table (LUT) can be configured to operate
in one of three general modes:
s Combinatorial logic mode
s Ripple mode
s Memory mode
The combinatorial logic mode uses a 64-bit look-up
table to implement Boolean functions. The two 5-bit
logic inputs, A[4:0] and B[4:0], and the C0 input are
Lucent Technologies Inc.
7

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Field-Programmable Gate Arrays

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