OR3LP26B Datasheet PDF - Agere Systems
| Part Number | OR3LP26B | |
| Description | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface | |
| Manufacturers | Agere Systems | |
| Logo |  |
|
|
There is a preview and OR3LP26B download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
Preview 1 page No Preview Available !
Data Sheet
March 2000
ORCA® OR3LP26B Field-Programmable System Chip (FPSC)
Embedded Master/Target PCI Interface
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of an FPGA-based design imple-
mentation, coupled with the high bandwidth of an
industry-standard PCI interface. The ORCA
OR3LP26B (a member of the Series 3+ FPSC family)
provides a full-featured 33/50/66 MHz, 32-/64-bit PCI
interface, fully designed and tested, in hardware, plus
FPGA logic for user-programmable functions.
PCI Bus Core Highlights
s Implemented in an ORCA Series 3 OR3L125B
base array, displacing the bottom ten rows of 28
columns.
s Core is a well-tested ASIC model.
s Fully compliant to Revision 2.2 of PCI Local Bus
specification.
s Operates at PCI bus speeds up to 66 MHz on a
32-/64-bit wide bus.
s Comprises two independent controllers for Master
and Target.
s Meets/exceeds all requirements for PICMG* Hot
Swap friendly silicon, full Hot Swap model, per the
CompactPCI* Hot Swap specification, PICMG 2.1
R1.0.
s PCI SIG Hot Plug (R1.0) compliant.
s Four internal FIFOs individually buffer both direc-
tions of both the Master and Target interfaces:
— Both Master FIFOs are 64 bits wide by 32 bits
deep.
— Both Target FIFOs are 64 bits wide by 16 bits
deep.
s Capable of no-wait-state, full-burst PCI transfers in
either direction, on either the Master or Target
interface. The dual 64-bit data paths extend into
the FPGA logic, permitting full-bandwidth, simulta-
neous bidirectional data transfers of up to
528 Mbytes/s to be sustained indefinitely.
s Can be configured to provide either two 64-bit
buses (one in each direction) to be multiplexed
between Master and Target, or four independent
32-bit buses.
s Provides many hardware options in the PCI core
that are set during FPGA logic configuration.
s Operates within the requirements of the PCI 5 V
and 3.3 V signaling environments and 3.3 V com-
mercial environmental conditions, allowing the
same device to be used in 5 V or 3.3 V PCI sys-
tems.
s FPGA is reconfigurable via the PCI interface's con-
figuration space (as well as conventionally), allow-
ing the FPGA to be field-updated to meet late-
breaking requirements of emerging protocols.
* PICMG and CompactPCI are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
Table 1. ORCA OR3LP26B PCI FPSC Solution—Available FPGA Logic
Device
OR3LP26B
Usable Gates†
Number of
LUTs
Number of
Registers
Max User
RAM
Max User
I/Os
60K—120K
4032
5304
64K
259
Array
Size
18 x 28
Number of
PFUs
504
† The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable
gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only
gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12
gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,
CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4
RAM (or 512 gates) per PFU.
|
| |
 
Data Sheet
March 2000
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Highlights (continued)
s Master:
— Generates all defined command codes except
interrupt acknowledge and special cycle.
— Capable of accessing its own local Target.
— Capable of acting as the system's configuration
agent by booting up with the Master logic
enabled.
— Supports multiple options for Master bus requests,
to increase PCI bus bandwidth.
— Supports single-cycle I/O space accesses.
— Provides option to delay PCI access until FIFO is
full on Master writes to increase PCI bandwidth.
— Supports programmable latency timer control.
s Target:
— Responds legally to all command codes: interrupt
acknowledge, special cycle, and reserved com-
mands ignored; memory read multiple and line
handled as memory read; memory write and
invalidate handled as memory write.
— Implements Target abort, disconnect, retry, and
wait cycles.
— Handles delayed transactions.
— Handles fast back-to-back transactions.
— Method of handling retries is programmable at
FPGA configuration to allow tailoring to different
Target data access latencies.
— Decodes at medium speed.
— Provides option to delay PCI access until FIFO is
full on Target reads to increase PCI bandwidth.
s Supports dual-address cycles (both as Master and
Target).
s Supports all six base address registers (BARs), as
either memory (32-bit or 64-bit) or I/O. Any legal
page size can be independently specified for each
BAR during FPGA configuration.
s Independent Master and Target clocks can be sup-
plied to the PCI FIFO interface from the FPGA-based
logic.
s Provides versatile clocking capabilities with FPGA
clocks sourced from PCI bus clock or elsewhere.
FIFO interface buffers asynchronous clock domains
between the PCI interface and FPGA-based logic.
s PCI interface timing: meets or exceeds 33 MHz,
50 MHz, and 66 MHz PCI requirements.
Parameter
Device Clock = > Out
Device Setup Time
Board Prop. Delay
Board Clock Skew
Total Budget
Load Capacitance
33 MHz
11.0 ns
7.0 ns
10.0 ns
2.0 ns
30.0 ns
50 pF
50 MHz
7.5 ns
4.5 ns
6.5 ns
1.5 ns
20.0 ns
50 pF
66 MHz
6.0 ns
3.0 ns
5.0 ns
1.0 ns
15.0 ns
10 pF
s Configuration options:
— Class code, revision ID.
— Latency timer.
— Cache line size.
— Subsystem ID.
— Subsystem vendor ID.
— Maximum latency, minimum grant.
— Interrupt line.
— Hot Plug/Hot Swap capability.
s Generates interrupts on intan as directed by the
FPGA.
s PCI I/O output drivers can be programmed for fast or
slew-limited operation.
s Automatically detects 5 V or 3.3 V PCI bus signaling
environment and provides appropriate I/O signaling,
under 3.3 V commercial conditions.
s Ideally suited for such applications as:
— PCI-based graphics/video/multimedia.
— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,
ATM, or other bus architectures.
— High-bandwidth data transfer in proprietary sys-
tems.
FPSC Highlights
s Implemented as an embedded core into the
advanced Series 3+ ORCA FPSC architecture.
s Allows the user to integrate the core with up to 120K
gates of programmable logic, all in one device, and
provides up to 259 user I/O pins in addition to the
PCI interface pins.
s FPGA portion retains all of the features of the ORCA
3 FPGA architecture:
— High-performance, cost-effective, 0.25 µm
5-level metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
Lucent Technologies Inc.
Lucent Technologies Inc.
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for OR3LP26B electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ OR3LP26B.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| OR3LP26B | The function is Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface. Agere Systems | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
OR3L
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||