OR3T20 Datasheet PDF - Agere Systems
| Part Number | OR3T20 | |
| Description | 3C and 3T Field-Programmable Gate Arrays | |
| Manufacturers | Agere Systems | |
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Data Sheet
June 1999
ORCA® Series 3C and 3T
Field-Programmable Gate Arrays
Features
s High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
s Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See ORCA
Series 3L FPGA documentation.)
s Up to 186,000 usable gates.
s Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
s Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
s Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
s Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
s Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
s Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
s Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
s Supplemental logic and interconnect cell (SLIC) provides
3-statable buffers, up to 10-bit decoder, and PAL*-like
AND-OR with optional INVERT in each programmable
logic cell (PLC), with over 50% speed improvement typi-
cal.
s Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
s TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
s Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
s Built-in boundary scan (IEEE †1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
s Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
s Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
s StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
s Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
s Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
* PAL is a trademark of Advanced Micro Devices, Inc.
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 3 (3C and 3T) FPGAs
Device
OR3T20
OR3T30
OR3C/3T55
OR3C/3T80
OR3T125
System
Gates‡
36K
48K
80K
116K
186K
LUTs Registers Max User RAM User I/Os Array Size
1152
1568
2592
3872
6272
1872
2436
3780
5412
8400
18K
25K
42K
62K
100K
196 12 x 12
228 14 x 14
292 18 x 18
356 22 x 22
452 28 x 28
Process
Technology
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
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Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Table of Contents
Contents
Page Contents
Page
Explicit Mode ........................................................... 90
Figure 54. Master Parallel Configuration Schematic 92
Figure 55. Master Serial Configuration Schematic ... 93
Figure 56. Asynchronous Peripheral Configuration .. 94
Figure 57. PowerPC/MPI Configuration Schematic .. 95
Figure 58. i960/MPI Configuration Schematic .......... 95
Figure 59. Configuration Through MPI ..................... 95
Figure 60. Readback Through MPI .......................... 96
Figure 61. Slave Serial Configuration Schematic ..... 97
Figure 62. Slave Parallel Configuration Schematic .. 97
Figure 63. Daisy-Chain Configuration Schematic ..... 98
Figure 64. Combinatorial PFU Timing .................... 105
Figure 65. Synchronous Memory Write
Characteristics ...................................................... 109
Figure 66. Synchronous Memory Read Cycle ........ 110
Figure 67. MPI PowerPC User Space Read Timing 117
Figure 68. MPI PowerPC User Space Write Timing 117
Figure 69. MPI PowerPC Internal Read Timing ..... 118
Figure 70. MPI PowerPC Internal Write Timing ...... 118
Figure 71. MPI i960 User Space Read Timing ....... 119
Figure 72. MPI i960 User Space Write Timing ....... 119
Figure 73. MPI i960 Internal Read Timing .............. 120
Figure 74. MPI i960 Internal Write Timing .............. 120
Figure 75. Boundary-Scan Timing Diagram ........... 122
Figure 76. ExpressCLK to Output Delay ................ 125
Figure 77. Fast Clock to Output Delay ................... 126
Figure 78. System Clock to Output Delay .............. 127
Figure 79. Input to ExpressCLK Setup/Hold Time .. 129
Figure 80. Input to Fast Clock Setup/Hold Time ..... 131
Figure 81. Input to System Clock Setup/Hold Time 132
Figure 82. General Configuration Mode Timing
Diagram .................................................................135
Figure 83. Master Serial Configuration Mode
Timing Diagram .....................................................136
Figure 84. Master Parallel Configuration Mode
Timing Diagram .....................................................137
Figure 85. Asynchronous Peripheral Configuration
Mode Timing Diagram ...........................................138
Figure 86. Slave Serial Configuration Mode
Timing Diagram .....................................................139
Figure 87. Slave Parallel Configuration Mode
Timing Diagram .....................................................140
Figure 88. Readback Timing Diagram ....................142
Figure 89. ac Test Loads ........................................143
Figure 90. Output Buffer Delays .............................143
Figure 91. Input Buffer Delays ................................143
Figure 92. Sinklim (TJ = 25 °C, VDD = 5.0 V) ..........144
Figure 93. Slewlim (TJ = 25 °C, VDD = 5.0 V) .........144
Figure 94. Fast (TJ °C, VDD = 5.0 V) ......................144
Figure 95. Sinklim (TJ = 125 °C, VDD = 4.5 V) ........144
Figure 96. Slewlim (TJ = 125 °C, VDD = 4.5 V) .......144
Figure 97. Fast (TJ = 125 °C, VDD = 4.5 V) ............144
Figure 98. Sinklim (TJ = 25 °C, VDD = 3.3 V) ..........145
Figure 99. Slewlim (TJ = 25 °C, VDD = 3.3 V) .........145
Figure 100. Fast (TJ = 25 °C, VDD = 3.3 V) ............145
Figure 101. Sinklim (TJ = 125 °C, VDD = 3.0 V) ......145
Figure 102. Slewlim (TJ = 125 °C, VDD = 3.0 V) .....145
Figure 103. Fast (TJ = 125 °C, VDD = 3.0 V) ..........145
Figure 104. Package Parasitics ..............................196
Lucent Technologies Inc.
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