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부품번호 OR3T55 기능
기능 3C and 3T Field-Programmable Gate Arrays
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OR3T55 데이터시트, 핀배열, 회로
Data Sheet
June 1999
ORCA® Series 3C and 3T
Field-Programmable Gate Arrays
Features
s High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
s Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See ORCA
Series 3L FPGA documentation.)
s Up to 186,000 usable gates.
s Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
s Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
s Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
s Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
s Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
s Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
s Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
s Supplemental logic and interconnect cell (SLIC) provides
3-statable buffers, up to 10-bit decoder, and PAL*-like
AND-OR with optional INVERT in each programmable
logic cell (PLC), with over 50% speed improvement typi-
cal.
s Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
s TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
s Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
s Built-in boundary scan (IEEE 1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
s Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
s Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
s StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
s Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
s Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
* PAL is a trademark of Advanced Micro Devices, Inc.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 3 (3C and 3T) FPGAs
Device
OR3T20
OR3T30
OR3C/3T55
OR3C/3T80
OR3T125
System
Gates
36K
48K
80K
116K
186K
LUTs Registers Max User RAM User I/Os Array Size
1152
1568
2592
3872
6272
1872
2436
3780
5412
8400
18K
25K
42K
62K
100K
196 12 x 12
228 14 x 14
292 18 x 18
356 22 x 22
452 28 x 28
Process
Technology
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.




OR3T55 pdf, 반도체, 판매, 대치품
ORCA Series 3C and 3T FPGAs
Data Sheet
June 1999
Contents
Table of Contents
Page Contents
Page
Characteristics ...................................................... 136
Table 62. Master Parallel Configuration Mode Timing
Characteristics ...................................................... 137
Table 63. Asynchronous Peripheral Configuration Mode
Timing Characteristics ........................................... 138
Table 64. Slave Serial Configuration Mode Timing
Characteristics ...................................................... 139
Table 65. Slave Parallel Configuration Mode
Timing Characteristics ........................................... 140
Table 66. Readback Timing Characteristics ........... 142
Table 67. Pin Descriptions ...................................... 149
Table 68. ORCA I/Os Summary ............................. 153
Table 69. Series 3 ExpressCLK Pins ..................... 154
Table 70. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 208-Pin
SQFP/SQFP2 Pinout ............................................ 155
Table 71. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 240-Pin
SQFP/SQFP2 Pinout ............................................ 161
Table 72. OR3T20, OR3T30, and OR3C/T55
256-Pin PBGA Pinout ............................................ 168
Table 73. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 352-Pin PBGA Pinout . 172
Table 74. OR3C/T80 and OR3T125 432-Pin
EBGA Pinout ......................................................... 182
Table 75. OR3T125 600-Pin EBGA Pinout ............ 187
Table 76. Plastic Package Thermal
Characteristics for the ORCA Series ..................... 195
Table 77. Package Coplanarity .............................. 196
Table 78. Package Parasitics ................................. 196
Table 79. Voltage Options ...................................... 206
Table 80. Temperature Options ............................. 206
Table 81. Package Options .................................... 206
Table 82. ORCA Series 3 Package Matrix ............. 206
Table 83. Speed Grade Options ............................. 206
Figures
Figure 1. OR3C/T55 Array ........................................ 10
Figure 2. PFU Ports .................................................. 11
Figure 3. Simplified PFU Diagram ............................ 12
Figure 4. Simplified F4 and F5 Logic Modes ............ 14
Figure 5. Softwired LUT Topology Examples ........... 15
Figure 6. Ripple Mode .............................................. 16
Figure 7. Counter Submode ..................................... 17
Figure 8. Multiplier Submode .................................... 18
Figure 9. Memory Mode ........................................... 19
Figure 10. Memory Mode Expansion Example—
128 x 8 RAM ........................................................... 20
Figure 11. SLIC All Modes Diagram ......................... 22
Figure 12. Buffer Mode ............................................. 22
Figure 13. Buffer-Buffer-Decoder Mode ................... 23
Figure 14. Buffer-Decoder-Buffer Mode ...................23
Figure 15. Buffer-Decoder-Decoder Mode ...............24
Figure 16. Decoder Mode .........................................24
Figure 17. Latch/FF Set/Reset Configurations .........26
Figure 18. Configurable Interconnect Point ..............27
Figure 19. Single PLC View of Inter-PLC Route
Segments ................................................................28
Figure 20. Multiple PLC View of Inter-PLC Routing .32
Figure 21. PLC Architecture .....................................35
Figure 22. OR3C/Txxx Programmable Input/Output
(PIO) Image from ORCA Foundry ...........................36
Figure 23. Fast-Capture Latch and Timing ...............39
Figure 24. PIO Input Demultiplexing .........................40
Figure 25. Output Multiplexing (OUT1OUT2 Mode) .42
Figure 26. Output Multiplexing
(OUT2OUTREG Mode) ...........................................42
Figure 27. PIC Architecture ......................................46
Figure 28. Interquad Routing ....................................47
Figure 29. hIQ Block Detail .......................................48
Figure 30. Top (TMID) Routing .................................49
Figure 31. PFU Clock Sources .................................50
Figure 32. ORCA Series 3 System Clock
Distribution Overview ..............................................51
Figure 33. PIC System Clock Spine Generation ......52
Figure 34. ExpressCLK and Fast Clock Distribution 53
Figure 35. Top CLKCNTRL Function Block ..............56
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry ..........................................................57
Figure 37. Boundary-Scan Interface .........................58
Figure 38. ORCA Series Boundary-Scan Circuitry
Functional Diagram .................................................60
Figure 39. TAP Controller State Transition Diagram 61
Figure 40. Boundary-Scan Cell ................................62
Figure 41. Instruction Register Scan Timing
Diagram ...................................................................63
Figure 42. MPI Block Diagram ..................................64
Figure 43. PowerPC/MPI ..........................................65
Figure 44. i960/MPI ..................................................66
Figure 45. PCM Block Diagram ................................72
Figure 46. PCM Functional Block Diagram ..............74
Figure 47. ExpressCLK Delay Minimization Using
the PCM ..................................................................76
Figure 48. Clock Phase Adjustment Using the PCM 83
Figure 49. FPGA States of Operation .......................85
Figure 50. Initialization/Configuration/Start-Up
Waveforms ..............................................................86
Figure 51. Start-Up Waveforms ................................88
Figure 52. Serial Configuration Data Format—
Autoincrement Mode ...............................................90
Figure 53. Serial Configuration Data Format—
4 Lucent Technologies Inc.

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OR3T55 전자부품, 판매, 대치품
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Description
FPGA Overview
The ORCA Series 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA Series from Lucent Technologies Micro-
electronics Group, with enhancements and innovations
geared toward today’s high-speed designs and tomor-
row’s systems on a single chip. Designed from the start
to be synthesis friendly and to reduce place and route
times while maintaining the complete routability of the
ORCA 2C/2T devices, Series 3 more than doubles the
logic available in each logic block and incorporates sys-
tem-level features that can further reduce logic require-
ments and increase system speed. ORCA Series 3
devices contain many new patented enhancements
and are offered in a variety of packages, speed grades,
and temperature ranges.
The ORCA Series 3 FPGAs consist of three basic ele-
ments: programmable logic cells (PLCs), programma-
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a sup-
plemental logic and interconnect cell (SLIC), local rout-
ing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL-like functions, and 3-state buffering can be per-
formed in the SLIC. The PICs provide device inputs
and outputs and can be used to register signals and to
perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4 sin-
gle- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform PAL-like functions. The 3-state drivers
in the SLIC and their direct connections to the PFU out-
puts make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for real-
world system performance.
Lucent Technologies Inc.
7

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OR3T55

3C and 3T Field-Programmable Gate Arrays

Agere Systems
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