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부품번호 ORT4622 기능
기능 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
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ORT4622 데이터시트, 핀배열, 회로
Preliminary Data Sheet
March 2000
ORCA® ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
s Implemented in an ORCA Series 3 FPGA array.
s Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
s No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
s High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
Table 1. ORCA ORT4622—Available FPGA Logic
s HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
s Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
s LVDS I/Os compliant with EIA*-644, support hot
insertion.
s 8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
s On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6 UIP-P at 250 kHz).
s Powerdown option of HSI receiver on a per-
channel basis.
s Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
s In-Band management and configuration.
s Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
s Built-in boundry scan (IEEE1149.1 JTAG).
s FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
s 1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
* EIA is a registered trademark of Electronic Industries Associa-
tion.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
ORT4622
Usable
System
Gates
60K—120K
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
Array Size
Number of
PFUs
259 18 x 28 504
‡ The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.




ORT4622 pdf, 반도체, 판매, 대치품
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Embedded Core Features (continued)
s Pseudo-SONET protocol including A1/A2 framing.
s SONET scrambling and descrambling for required
ones density (optional).
s Selected transport overhead (TOH) bytes insertion
and extraction for interdevice communication via the
TOH serial link.
FPSC Highlights
s Implemented as an embedded core in the ORCA
Series 3+ FPSC architecture.
s Allows the user to integrate the core with up to 120K
gates of programmable logic (all in one device) and
provides up to 242 user I/Os in addition to the
embedded core I/O pins.
s FPGA portion retains all of the features of the ORCA
Series 3 FPGA architecture:
— High-performance, cost-effective, 0.25 µm, 5-level
metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, as well as for a general-
purpose interface to the FPGA. Glueless interface
to i960and PowerPC processors with user-
configurable address space provided.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex
functions, such as digital phase-locked loops,
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per
device.
— True internal 3-state, bidirectional buses with
simple control provided by the SLIC.
— 32 x 4 RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Built-in boundary scan (IEEE 1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
s High-speed, on-chip interface provided between
FPGA logic and embedded core to reduce bottle-
necks typically found when interfacing off-chip.
Software Support
s Supported by ORCA Foundry software and third-
party CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with the
embedded core functions.
s Embedded core configuration options and simulation
netlists generated by FPSC Configuration Manager
utility.
* PAL is a trademark of Advanced Micro Devices, Inc.
i960 is a registered trademark of Intel Corporation.
PowerPC is a registered trademark of International Business
Machines Corporation.
4 LuLcuecnetnTteTcehcnhonloolgoigeisesInIcn.c.

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ORT4622 전자부품, 판매, 대치품
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Description (continued)
Routing
PIC Logic
The Series 3 PIC addresses the demand for ever-
increasing system clock speeds. Each PIC contains
four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA Series 2 capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is the same as the
ORCA Series 3 buffer.
System Features
The Series 3 also provides system-level functionality
by means of its dual-use microprocessor interface
(MPI) and its innovative programmable clock manager
(PCM). These functional blocks allow for easy glueless
system interfacing and the capability to adjust to vary-
ing conditions in today’s high-speed systems. Since
these and all other Series 3 features are available in
every Series 3+ FPSC, they can also interface to the
embedded core providing for easier system integration.
The abundant routing resources of ORCA Series 3
FPGA logic are organized to route signals individually
or as buses with related control signals. Clocks are
routed on a low-skew, high-speed distribution network
and may be sourced from PLC logic, externally from
any I/O pad, or from the very fast ExpressCLK pins.
ExpressCLKs may be glitchlessly and independently
enabled and disabled with a programmable control sig-
nal using the StopCLK feature. The improved PIC rout-
ing resources are now similar to the patented intra-PLC
routing resources and provide great flexibility in moving
signals to and from the PIOs. This flexibility translates
into an improved capability to route designs at the
required speeds when the I/O signals have been
locked to specific pins.
Configuration
The FPGA logic’s functionality is determined by inter-
nal configuration RAM. The FPGA logic’s internal ini-
tialization/configuration circuitry loads the configuration
data at powerup or under system control. The RAM is
loaded by using one of several configuration modes,
including serial EEPROM, the microprocessor inter-
face, or the embedded function core.
More Series 3 Information
For more information on Series 3 FPGAs, please refer
to the Series 3 FPGA data sheet, available on the
ORCA worldwide website or by contacting Lucent
Technologies as directed on the back of this data
sheet.
Lucent Technologies Inc.
Lucent Technologies Inc.
7

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부품번호상세설명 및 기능제조사
ORT4622

Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver

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