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OZ6833B 데이터시트 PDF




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부품번호 OZ6833B 기능
기능 ACPI CardBus Controller
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OZ6833B 데이터시트, 핀배열, 회로
FEATURES
Single-chip CardBus host adapter
Supports 2 PCMCIA 1.0 and JEIDA 4.2 R2 cards or 2
CardBus cards
ACPI-PCI Bus Power Management Interface
Specification Rev1.0 Compliant
Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#
Compliant with PCI specification v2.1S, 1998 PC Card
Standard 7.0
Yenta PCI to PCMCIA CardBus Bridge register
compatible
ExCA (Exchangeable Card Architecture) compatible
registers map-able in memory and I/O space
Intel 82365SL PCIC Register Compatible
Supports PCMCIA_ATA Specification
Supports 5V/3.3V PC Cards and 3.3V CardBus cards
Supports two PC Card or CardBus slots with hot
insertion and removal
Supports multiple FIFOs for PCI/CardBus data transfer
Supports Direct Memory Access for PC/PCI and
PC/Way on PC Card socket
Programmable interrupt protocol: PCI, PCI+ISA,
PCI/Way, or PC/PCI interrupt signaling modes
Win’98 IRQ and PC-97/98 compliant
Parallel or Serial interface for socket power control
devices (TI or Micrel)
Zoomed Video Support
Integrated PC 98 – Subsystem Vendor ID support, with
auto lock bit
LED Activity Pins
ORDERING INFORMATION
OZ6833T – 208 pin TQFP
OZ6833B – 208 pin Mini-BGA
GENERAL DESCRIPTION
The OZ6833 ACPI CardBus controller provides a high
performance, synchronous, 32-bit, bus master/target
interface between computers and plug in PC Cards.
CardBus is the new 32-bit interface standard of Personal
Computer Memory Card International Association,
PCMCIA. The CardBus provides 32-bit interface with
multiplexed address and data lines. This will allow the
addition of high performance computer system
enhancements and new functions in a user-friendly way.
Further, the expansion capability of the CardBus will
provide benefits to the end user. CardBus is intended to
OZ6833
ACPI CardBus Controller
support “temporal” add-in functions on PC Cards, such as
Memory cards, Network interfaces, FAX/Modems and other
wireless communication cards, etc. The high performance
and capability of the CardBus interface will enable further
development of many new functions and applications.
The OZ6833 CardBus controller is a 33MHz PCI compliant
master/target device that attaches to the PCI bus and
manages two PC Card sockets. The PC Card sockets
support both 3.3V / 5V versions of 8/16-bit PCMCIA R2
card or 32-bit CardBus card. R2 card support is compatible
with the Intel 82365SL PCIC controller. CardBus card
support is fully compatible with the 1998 PC Card Standard
V7.0. The OZ6833 is a stand alone device. It does not
require an additional buffer chip for the two PC Card socket
interface. The OZ6833 is implemented with a complex
multiple FIFO data buffer for the PCI and CardBus interface
to provide better PCI/CardBus access.
The FIFO buffers allow the bridge to accept data from a
target bus while moving data to it, facilitating deadlock
prevention. In addition, the OZ6833 is designed with
dynamic PC Card hot insertion and removal and auto
configuration capabilities.
The OZ6833 ACPI CardBus Controller provides the power
saving mixed 5V / 3.3V capability. An advance CMOS
process minimizes system power consumption. The device
also provides a power-down mode, allowing host software
to reduce power consumption further while stopping
internal clock distribution and the clocks on PC Card
sockets. The OZ6833 is not only a CardBus bridge, but
also a socket controller. The OZ6833 supports two master
devices and arbitrates the priority of each. Further, it
supports inter CardBus direct data transfer. The register set
in the OZ6833 is the superset of the OZ67xx register set,
assuring full compatibility with existing socket/card-services
software and PC-card applications. The OZ6833 provides
the most advanced design flexibility for the PC Card
interface in notebook computer design.
To enhance the performance between the PCI bus and any
CardBus card, two buffers (each composed of 16 double
words) are added on both sides going from PCI to CardBus
or the other way around. By implementing these buffers,
the OZ6833 will not refuse data from a target bus while
moving data and preventing deadlock situations.
In order to allow maximum flexibility for system designers,
the CINT# of the PC card 32-bit may be programmed to
steer to either INTA# or INTB# of the PCI bus. Further, the
interrupts may be programmed to route through the bridge
to either PCI INT lines or IRQ interrupts on the ISA bus.
04/25/00
Copyright 1999 by O2Micro
OZ6833-DS-1.55
All Rights Reserved
Page 1




OZ6833B pdf, 반도체, 판매, 대치품
PIN DIAGRAM - 208 PIN TQFP
OZ6833
PCI_CLK
PCI_GNT#
PCI_REQ#
AD31
AD30
PCI_VCC
AD29
AD28
AD27
AD26
AD25
AD24
C/BE3#
CORE_GND
IDSEL
AD23
AD22
AD21
AD20
AD19
PCI_VCC
AD18
AD17
AD16
C/BE2#
CORE_GND
FRAME#
CORE_GND
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
C/BE1#
PCI_VCC
AD15
AD14
AD13
AD12
AD11
AD10
CORE_GND
AD9
AD8
C/BE0#
AD7
AD6
PCI_VCC
AD5
AD4
2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11
1
2
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
6
4
6
3
6
2
6
1
6
0
5
9
5 5 156
8 7 155
3 154
4 153
5 152
6 151
7 150
8 149
9 148
10 147
11 146
12 145
13 144
14 143
15 142
16 141
17 140
18 139
19 138
20 137
21 136
22 135
23
24
O2Micro, Inc.
134
133
25
26
OZ6833
132
131
27 130
28 129
29 128
30 127
31 126
32 125
33 124
34 123
35 122
36 121
37 120
38 119
39 118
40 117
41 116
42 115
43 114
44 113
45 112
46 111
47 110
48 109
49 108
50 107
51
52
555
5
5
5
5
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
77
7
7
7
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
99
9
1
0
1
0
1
0
1
0
1
0
106
105
345 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 56 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 78 9 0 1 2 3 4
B_IOWR#/CAD15
B_A9/CAD14
B_IORD#/CAD13
B_A11/CAD12
B_VS1/CVS1
B_OE#/CAD11
B_CE2#/CAD10
B_A10/CAD9
B_D15/CAD8
B_CE1#/CCBE0#
B_VPP_VCC
B_D14/RFU
B_D7/CAD7
B_SOCKET_VCC
B_D13/CAD6
B_D6/CAD5
B_D12/CAD4
B_D5/CAD3
B_D11/CAD2
B_D4/CAD1
B_CD1#/CCD1#
B_D3/CAD0
CORE_VCC
LED_OUT/SKT_ACTIVITY
SCLK/A_VCC5#
SDATA/B_VCC3#
SLATCH/B_VCC_5#
CORE_GND
SPKR_OUT#
AUX_VCC
A_CD2#/CCD2#
A_WP/CCLKRUN#
A_D10/CAD31
A_D2/RFU
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27
A_BVD1/STSCHG
A_SOCKET_VCC
A_A0/CAD26
A_VPP_VCC
A_BVD2/CAUDIO
A_A1/CAD25
A_REG#/CCBE3#
A_A2/CAD24
A_INPACK#/CREQ#
A_A3/CAD23
A_WAIT#/CSERR#
A_A4/CAD22
A_RESET/CRESET#
A_A5/CAD21
OZ6833-DS-1.55
Page 4

4페이지










OZ6833B 전자부품, 판매, 대치품
OZ6833
Pin Name
INTB#
SOUT#/
IRQSER
SIN#
GNT#
REQ#
LOCK#
PCI_VCC
Description
PCI Bus Interrupt B: This output
indicates a programmable interrupt
request generated from any of a number
of card actions. Although there is no
specific mapping requirement for
connecting interrupt lines from the
OZ6833 to the system, a common use is
to connect this pin to the system PCI bus
INTB# signal.
SOUT#/IRQSER: In PC/PCI Serial
Interrupt Signaling mode, this pin is the
serial interrupt output, SOUT#. In PC/Way
mode, this pin is the IRQ serializer pin to
the interrupt controller.
SIN#: In PC/PCI Serial Input Signaling
mode, this pin is the serial interrupt input,
SIN#.
Grant: This signal indicates that access
to the bus has been granted.
Request: This signal indicates to the
arbiter that the OZ6833 requests use of
the bus.
PCI LOCK#: This signal is used by a PCI
master to perform a locked transaction to
a target memory. LOCK# is used to
prevent more than one master from using
a particular system resource.
PCI Bus VCC: These pins can be
connected to either a 3.3- or 5-volt power
supply. The PCI bus interface pin outputs
listed in this table (Table 2-1) will operate
at the voltage applied to these pins,
independent of the voltage applied to
other OZ6833 pin groups.
Pin Number
TQFP
BGA
204 C4
205 B3
206 A2
2 D4
3 C2
58 U3
6, 21, 37, 50 D3, G1, L1, T1
Input
-
TTL
TTL
TTL
N/A
TTL
-
PCMCIA Sockets Interface Pins
Socket A pin number --- Socket B pin number
Name1
-REG#/
CCBE3#
A[25:24]/
CAD[19, 17]
A23/
CFRAME#
Description2
Register Access: During PCMCIA
memory cycles, this output chooses
between attribute and common
memory. During I/O cycles for non-DMA
transfers, this signal is active (low).
During ATA mode, this signal is always
inactive. For DMA cycles on the
OZ6833 to a DMA-capable card, -REG
is inactive during I/O cycles to indicate
DACK to the PCMCIA card.
CardBus Command Byte Enable: In
CardBus mode, this pin is the CCBE3#.
PCMCIA socket address 25:24 outputs.
CardBus Address/Data: CardBus
mode, these pins are the CAD bits 19
and 17.
PCMCIA socket address 23 output.
CardBus Frame: In CardBus mode,
this pin is the CFRAME# signal.
Pin Number
Socket A
Socket B
TQFP BGA TQFP BGA
112 P15 188
D7
102, R15,
99 U15
176,
174
D10,
B11
96 U14 172 D11
Qty
1
2
1
Type
TO
Power
Rail
4
Drive
PCI Spec
I/O 4 PCI Spec
I/O 4 PCI Spec
I 4 PCI Spec
TO 4 PCI Spec
I/O 4 PCI Spec
PWR
-
I/O Pwr Drive
I/O 2 or 3 CardBus
spec.
I/O 2 or 3 CardBus
spec.
I/O 2 or 3 CardBus
spec.
OZ6833-DS-1.55
Page 7

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관련 데이터시트

부품번호상세설명 및 기능제조사
OZ6833

ACPI CardBus Controller

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ETC
OZ6833B

ACPI CardBus Controller

ETC
ETC

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