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부품번호 P28F001BX-B120 기능
기능 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
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P28F001BX-B120 데이터시트, 핀배열, 회로
1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
Y High-Integration Blocked Architecture
One 8 KB Boot Block w Lock Out
Two 4 KB Parameter Blocks
One 112 KB Main Block
Y 100 000 Erase Program Cycles Per
Block
Y Simplified Program and Erase
Automated Algorithms via On-Chip
Write State Machine (WSM)
Y SRAM-Compatible Write Interface
Y Deep Power-Down Mode
0 05 mA ICC Typical
0 8 mA IPP Typical
Y 12 0V g5% VPP
Y High-Performance Read
70 75 ns 90 ns 120 ns 150 ns
Maximum Access Time
5 0V g10% VCC
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Advanced Packaging JEDEC Pinouts
32-Pin PDIP
32-Lead PLCC TSOP
Y ETOXTM II Nonvolatile Flash
Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y Extended Temperature Options
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase These devices aid the system designer by combining the
functions of several components into one making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor
interface
The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of
8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment
conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s
MCS -186 family 80286 i386TM i486TM i860TM and 80960CA With exactly the same memory segmentation
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory
such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless
otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document
The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds low power consumption and immunity to noise Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown
mode lowers power consumption to 0 25 mW typical through VCC crucial in laptop computer handheld instru-
mentation and other low-power applications The RP power control input also provides absolute data protec-
tion during system powerup or power loss
Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality reliability and cost-effectiveness
NOTE The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290406-007




P28F001BX-B120 pdf, 반도체, 판매, 대치품
28F001BX-T 28F001BX-B
Figure 4 PLCC Lead Configuration
290406 – 4
APPLICATIONS
The 28F001BX flash ‘boot block’ memory augments
the non-volatility in-system electrical erasure and
reprogrammability of Intel’s standard flash memory
by offering four separately erasable blocks and inte-
grating a state machine to control erase and pro-
gram functions The specialized blocking architec-
ture and automated programming of the 28F001BX
provide a full-function non-volatile flash memory
ideal for a wide range of applications including PC
boot BIOS memory minimum-chip embedded pro-
gram memory and parametric data storage The
28F001BX combines the safety of a hardware-pro-
tected 8-KByte boot block with the flexibility of three
separately reprogrammable blocks (two 4-KByte pa-
rameter blocks and one 112-KByte code block) into
one versatile cost-effective flash memory Addition-
ally reprogramming one block does not affect code
stored in another block ensuring data integrity
The flexibility of flash memory reduces costs
throughout the life cycle of a design During the early
stages of a system’s life flash memory reduces pro-
totype development and testing time allowing the
system designer to modify in-system software elec-
trically versus manual removal of components Dur-
ing production flash memory provides flexible firm-
ware for just-in-time configuration reducing system
inventory and eliminating unnecessary handling and
less reliable socketed connections Late in the life
cycle when software updates or code ‘‘bugs’’ are
often unpredictable and costly flash memory reduc-
es update costs by allowing the manufacturers to
send floppy updates versus a technician Alterna-
tively remote updates over a communication link are
possible at speeds up to 9600 baud due to flash
memory’s fast programming time
4

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P28F001BX-B120 전자부품, 판매, 대치품
28F001BX-T 28F001BX-B
BUS OPERATION
Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles
Read
The 28F001BX has three read modes The memory
can be read from any of its blocks and information
can be read from the Intelligent Identifier or the
Status Register VPP can be at either VPPL or VPPH
The first task is to write the appropriate read mode
command to the Command Register (array Intelli-
gent Identifier or Status Register) The 28F001BX
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown
The 28F001BX has four control pins two of which
must be logically active to obtain data at the outputs
Chip Enable (CE ) is the device selection control
and when active enables the selected memory de-
vice Output Enable (OE ) is the data input output
(DQ0 – DQ7) direction control and when active
drives data from the selected memory onto the I O
bus RP and WE must also be at VIH Figure 12
illustrates read bus cycle waveforms
Output Disable
With OE at a logic-high level (VIH) the device out-
puts are disabled Output pins (DQ0 – DQ7) are
placed in a high-impedance state
Standby
CE at a logic-high level (VIH) places the 28F001BX
in standby mode Standby operation disables much
of the 28F001BX’s circuitry and substantially reduc-
es device power consumption The outputs (DQ0
DQ7) are placed in a high-impedance state indepen-
dent of the status of OE If the 28F001BX is dese-
lected during erase or program the device will
continue functioning and consuming normal active
power until the operation is completed
Deep Power-Down
The 28F001BX offers a 0 25 mW VCC power-down
feature entered when RP is at VIL During read
modes RP low deselects the memory places out-
put drivers in a high-impedance state and turns off
all internal circuits The 28F001BX requires time
tPHQV (see AC Characteristics-Read Only Opera-
tions) after return from power-down until initial mem-
ory access outputs are valid After this wakeup inter-
val normal operation is restored The Command
Register is reset to Read Array and the Status Reg-
ister is cleared to value 80H upon return to normal
operation
During erase or program modes RP low will abort
either operation Memory contents of the block be-
ing altered are no longer valid as the data will be
partially programmed or erased Time tPHWL after
RP goes to logic-high (VIH) is required before an-
other command can be written
Mode
Read
Output Disable
Standby
Deep Power Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
Table 2 28F001BX Bus Operations
Notes RP CE OE WE
1 2 3 VIH VIL VIL VIH
2 VIH VIL VIH VIH
2
VIH VIH
X
X
2 VIL X X X
2 3 4 VIH VIL VIL VIH
2 3 4 5 VIH VIL VIL VIH
2 6 7 8 VIH VIL VIH VIL
A9 A0 VPP
XX X
XX X
DQ0 – 7
DOUT
High Z
XX X
High Z
XX X
High Z
VID VIL X
89H
VID VIH X 94H 95H
XX X
DIN
NOTES
1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not programmed or erased
2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP
3 See DC Characteristics for VPPL VPPH VHH and VID voltages
4 Manufacturer and device codes may also be accessed via a Command Register write sequence Refer to Table 3 A1 – A8
A10 – A16 e VIL
5 Device ID e 94H for the 28F001BX-T and 95H for the 28F001BX-B
6 Command writes involving block erase or byte program are successfully executed only when VPP e VPPH
7 Refer to Table 3 for valid DIN during a write operation
8 Program or erase the boot block by holding RP at VHH or toggling OE to VHH See AC Waveforms for program erase
operations
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부품번호상세설명 및 기능제조사
P28F001BX-B120

1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY

Intel Corporation
Intel Corporation

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