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부품번호 | P2V28S20ATP-75 기능 |
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기능 | 128Mb SDRAM Specification | ||
제조업체 | Vanguard International Semiconductor | ||
로고 | |||
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
128Mb SDRAM Specification
P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8
JULY.2000
MIRA TECHNOLOGY INC.
8F.,68,SEC.3,NANKING E.RD.,TAIPEI,TAIWAN,R.O.C.
TEL:886-2-25170055.25170066
FAX:886-2-25174575
Rev.2.2
BLOCK DIAGRAM
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
DQ0-7
I/O Buffer
Memory Array
4096 x1024 x8
Cell Array
Bank #0
Memory Array
4096 x1024 x8
Cell Array
Bank #1
Memory Array
4096 x1024 x8
Cell Array
Bank #2
Memory Array
4096 x1024 x8
Cell Array
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-11 BA0,1
CLK CKE
/CS /RAS
/CAS
/WE DQM
Note:This figure shows the P2V28S30ATP
The A2V28S20ATP configuration is 4096x2048x4 of cell array and DQ0-3
The A2V28S40ATP configuration is 4069x512x16 of cell array and DQ0-15
Type Designation Code
P2 V 28 S 3 0 A TP -8
Access Item
Package Type
Process Generation
Function
Organization
Synchronous DRAM
Density
Interface
PSC DRAM
-7 : 7 ns (143MHz/3-3-3)
-75 : 7.5ns (100MHz/2-2-2 or 133MHz/3-3-3)
-8 : 8 ns (100MHz/2-2-2 or 125MHz/3-3-3)
TP : TSOP(II)
A : 2nd generation
0 : Random Column
2 : x4, 3 : x8, 4: x16
128 :128Mbit
V :LVTTL
JULY.2000
Page-3
Rev.2.2
4페이지 128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
Row Address Entry &
Bank Active
Single Bank Precharge
Precharge All Banks
Column Address Entry
&Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
MNEMONIC CKE CKE /CS /RAS /CAS /WE BA0,1 A1 1 A1 0 A0-9
n-1 n
DESEL
H XHX XX X XXX
NOP
H X L HHH X X X X
ACT
H X L L HH V V V V
PRE
PREA
H X L L HL V X LX
H X L L HL X XHX
WRIT E
HXLHLL VVLV
WRITE A
READ
HX
HX
LH
LH
LL V
LHV
VHV
VLV
READA
REFA
H X L HLH V VHV
HHLL LHXXXX
REFS
HL LL LHXXXX
REFSX
L HHX XX X XXX
L H L HHH X X X X
Burst Terminate
TBST
HX L HHL XX XX
Mode Register Set
MR S
H X L L L L L L L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
JULY.2000
Page-6
Rev.2.2
7페이지 | |||
구 성 | 총 51 페이지수 | ||
다운로드 | [ P2V28S20ATP-75.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
P2V28S20ATP-7 | 128Mb SDRAM Specification | Vanguard International Semiconductor |
P2V28S20ATP-75 | 128Mb SDRAM Specification | Vanguard International Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |