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P4C1682I-sspt 데이터시트 PDF




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기능 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
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P4C1682I-sspt 데이터시트, 핀배열, 회로
P4C1681, P4C1682
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
P4C1681, P4C1682
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 20/25/35ns (P4C1682 Military)
Low Power Operation (Commercial)
– 715 mW Active – 12, 15
– 550 mW Active – 20/25/35
– 193 mW Standby (TTL Input)
– 83 mW Standby (CMOS Input)
Single 5V ± 10%Power Supply
Separate Inputs and Outputs
– P4C1681 Input Data at Outputs during Write
– P4C1682 Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOIC
– 24-Pin 300 mil SOJ
– 24-Pin CERDIP
– 28-Pin LCC (450 mil x 450 mil)
DESCRIPTION
The P4C1681 and P4C1682 are 16,384-bit (4K x 4) ultra
high speed static RAMs similar to the P4C168, but with
separate data I/O pins. The P4C1681 features a
transparent write operation; the outputs of the P4C1682
are in high impedance during the write cycle. All devices
have low power standby modes. The RAMs operate from
a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby. For the P4C1682 and
P. 4C1681, power is only 83 mW standby with CMOS input
levels.
The P4C1681 and P4C1682 are available in 24-pin 300
mil DIP and SOIC packages providing excellent board
level densities. The P4C1682 is also available in a 28-pin
LCC package.
FUNCTIONAL BLOCK DIAGRAM
A
(7)
A
I1
I2
I3
I4
ROW
SELECT
INPUT
DATA
CONTROL
16,384-BIT
MEMORY
ARRAY
COLUMN I/O
POWER
DOWN
COLUMN
SELECT
CE
WE A A
(5)
P4C1682
P4C1681
O1
O2
O3
O4
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
A7
I1
I2
CE
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 A11
22 A10
4
26
21 A9
20 A8
A4
A5
5 32
2 8 2 7 25
6 1 24
19 I4
NC 7
23
18 I 3
17 O4
16 O3
15 O2
14 O1
NC 8
A6 9
A7 10
I1 11
13 14 15 16 17
12
22
21
20
19
18
13 WE
A9
A8
I4
NC
NC
I3
O4
DIP (P4,D4), SOIC (S4), SOJ (J4)
TOP VIEW
LCC (L5-1)
TOP VIEW
Means Quality, Service and Speed
1Q97
41




P4C1682I-sspt pdf, 반도체, 판매, 대치품
P4C1681, P4C1682
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Symbol
Parameter
-12 -15
-20
Min Max Min Max Min Max
-25 -35
Min Max Min Max
Unit
tRC Read Cycle Time 12 15 20 25 35 ns
tAA Address Access
Timens
12 15 20 25 35 ns
tAC Chip Enable
Access Time
12 15 20 25 35 ns
tOH Output Hold from 2 2 3 3 3 ns
Address Change
tLZ Chip Enable to
2
23
3
3 ns
Output in Low Z
tHZ Chip Disable to
Output in High Z
6 7 9 10 15 ns
t
Read Command
0
00
0
0 ns
RCS
Setup Time
tRCH Read Command
0
00
0
0 ns
Hold Time
tPU Chip Enable to
0
00
0
0 ns
Power Up Time
t Chip Disable to
12 15 20 25 25 ns
PD
Power Down Time
1552 Tbl 10
READ CYCLE NO. 1 (ADDRESS controlled)(5, 6)
(9)
t RC
ADDRESS
DATA OUT
t OH
PREVIOUS DATA VALID
t AA
DATA VALID
READ CYCLE NO. 2 (CE controlled)(5, 7)
tRC
CE
DATA OUT
VCC SUPPLY
CURRENT
I CC
I SB
WE
t AC
t LZ (3)
t PU
t RCS
Notes:
5. WE is HIGH for READ cycle.
6. CE, OE are LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with, CE
transition LOW.
t HZ (8)
DATA VALID
t PD
HIGH IMPEDANCE
t RCH
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
44

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P4C1682I-sspt

ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS

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