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PDF P4C188 Data sheet ( Hoja de datos )
| Número de pieza | P4C188 | |
| Descripción | ULTRA HIGH SPEED 16K x 4 STATIC | |
| Fabricantes | ETC | |
| Logotipo |  |
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P4C188/P4C188L
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
P4C188/188L
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C188
– 15 mW Standby (CMOS Input)
(P4C188L Military)
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
(P4C188L Military)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290 x 490 mil LCC
DESCRIPTION
The P4C188 and P4C188L are 65,536-bit ultra high speed
static RAMs organized as 16K x 4. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAMs operate from a single 5V±10% tolerance power
supply. With battery backup, data integrity is maintained for
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption to a low 715mW
active, 193mW standby and only 5mW in the P4C188L
version.
The P4C188 and P4C188L are available in 22-pin 300 mil
DIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid-
ing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
A
(8)
A
I/O 1
I/O 2
I/O 3
I/O 4
ROW
SELECT
INPUT
DATA
CONTROL
65,536-BIT
MEMORY
ARRAY
COLUMN I/O
COLUMN
SELECT
CE
AA
(6)
WE
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
GND
1
2
3
4
5
6
7
8
9
10
11
22 V CC
21 A 13
20 A 12
19 A 11
18 A 10
17 A 9
16 I/O 4
15 I/O 3
14 I/O 2
13 I/O 1
12 WE
2 21
A2 3
22 20
1
A3 4
19
A4 5
18
A5 6
17
A6 7
16
A7 8
15
A 8 9 11 12 14
10 13
A 12
A 11
A 10
A9
I/O 4
I/O 3
I/O 2
DIP (P3, D3)
TOP VIEW
LCC (L3)
TOP VIEW
For SOJ pin configuration, please see Selection Guide Page.
Means Quality, Service and Speed
1Q97
63
1 page  
P4C188/188L
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
-10 -12 -15 -20 -25 -35 -45
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
t
WC
Write Cycle Time 10
12
13 20
25
35
45 ns
tCW Chip Enable
7
8
10 13 15 25 35 ns
Time to
End of Write
t
AW
Address Valid
7
8
10 15 20 25 35 ns
to End of Write
tAS Address
0 0 0 0 0 0 0 ns
Set-up Time
t Write Pulse
8
9
10 13 15 25 35 ns
WP
Width
t
AH
Address Hold
0
0
00
0
0
0 ns
Time from
End of Write
t Data Valid to
DW
End of Write
tDH Data Hold
Time
5
0
6
0
7 8 10 15 20 ns
0 0 0 0 5 ns
tWZ Write Enable
to Ourput in
High Z
5 6 6 8 10 15 20 ns
tDW Output Active
from End
of Write
2
2
22
23
3 ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9)
(11)
t WC
ADDRESS
CE
t CW
t AW
t WP
t WR
t AH
WE
DATA IN
DATA OUT
t AS
DATA UNDEFINED
t
(12)
WZ
t DW
DATA VALID
t DH
t
(10,
OW
12)
HIGH IMPEDANCE
Notes:
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
12. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
67
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet P4C188.PDF ] | |
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