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S93662 데이터시트 PDF




ETC에서 제조한 전자 부품 S93662은 전자 산업 및 응용 분야에서
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부품번호 S93662 기능
기능 Voltage Monitor and Reset Controller
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S93662 데이터시트, 핀배열, 회로
SUMMIT
MICROELECTRONICS, Inc.
Precision Supply-Voltage Monitor and Reset Controller
S93662/S93663
FEATURES
• Precision Monitor & RESET Controller
— RESET and RESET Outputs
— Guaranteed RESET Assertion to VCC = 1V
— 200ms Reset Pulse Width
— Internal 1.26V Reference with ±1% Accuracy
— ZERO External Components Required
• Memory
— 4K-bit Microwire Memory
— S93662
– Internally Ties ORG Low
– 100% Compatible With all 8-bit
Implementations
– Sixteen Byte Page Write Capability
— S93663
– Internally Ties ORG High
– 100% Compatible With all 16-bit
Implementations
– Eight Word Page Write Capability
OVERVIEW
The S93662 and S93663 are precision power supervi-
sory circuits providing both active high and active low
reset outputs.
Both devices have 4k-bits of E2PROM memory that is
accessible via the industry standard microwire bus. The
S93662 is configured with an internal ORG pin tied low
providing a 8-bit byte organization and the S93663 is
configured with an internal ORG pin tied high providing
a 16-bit word organization. Both the S93662 and
S93663 have page write capability. The devices are
designed for a minimum 100,000 program/erase cycles
and have data retention in excess of 100 years.
BLOCK DIAGRAM
VCC
8
5kHz
OSCILLATOR
RESET
PULSE
GENERATOR
6 RESET#
CS 1
SK 2
DI 3
+ VTRIP
RESET
CONTROL
1.26V
MODE
DECODE
ADDRESS
DECODER
WRITE
CONTROL
7 RESET
DO 4
5
GND
DATA I/O
E2PROM
MEMORY
ARRAY
2012 T BD 2.0
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2012 2.0 4/18/00
Characteristics subject to change without notice
1




S93662 pdf, 반도체, 판매, 대치품
S93662/S93663
writing or clearing of the device. Data can be read
normally from the device regardless of the write enable/
disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of 250ns
(tCSMIN). The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the S93662/663 can be determined by select-
ing the device and polling the DO pin. Once cleared, the
contents of all memory bits return to a logical 1state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
250ns (tCSMIN). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the S93662/663 can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Page Write
93662 - Assume WEN has been issued. The host will
then take CS high, and begin clocking in the start bit,
write command and 9-bit byte address immediately
followed by the first byte of data to be written. The host
can then continue clocking in 8-bit bytes of data with
each byte to be written to the next higher address.
Internally the address pointer is incremented after
receiving each group of eight clocks; however, once
the address counter reaches x xxxx 1111 it will roll over
to x xxxx 0000 with the next clock. After the last bit is
clocked in no internal write operation will occur until CS
is brought low.
93663 - Assume WEN has been issued. The host will
then take CS high, and begin clocking in the start bit,
write command and 8-bit byte address immediately
followed by the first 16-bit word of data to be written.
The host can then continue clocking in 16-bit words of
data with each word to be written to the next higher
address. Internally the address pointer is incremented
after receiving each group of sixteen clocks; however,
once the address counter reaches xxxx x111 it will roll
over to xxxx x000 with the next clock. After the last bit
is clocked in no internal write operation will occur until
CS is brought low.
Continuous Read
This begins just like a standard read with the host
issuing a read instruction and clocking out the data
byte [word]. If the host then keeps CS high and
continues generating clocks on SK, the S93662/663
will output data from the next higher address location.
The S93662/663 will continue incrementing the ad-
dress and outputting data so long as CS stays high. If
the highest address is reached, the address counter
will roll over to address 0000. . CS going low will reset
the instruction register and any subsequent read must
be initiated in the normal manner of issuing the com-
mand and address.
2012 2.0 4/18/00
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S93662 전자부품, 판매, 대치품
S93662/S93663
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................................................................................................................................... 55°C to +125°C
Storage Temperature ......................................................................................................................................... 65°C to +150°C
Voltage on any Pin with Respect to Ground(1) ............................................................................................ 2.0V to +VCC +2.0V
VCC with Respect to Ground .................................................................................................................................. 2.0V to +7.0V
Package Power Dissipation Capability (Ta = 25°C) ............................................................................................................. 1.0W
Lead Soldering Temperature (10 seconds) ........................................................................................................................ 300°C
Output Short Circuit Current(2) ........................................................................................................................................... 100mA
*COMMENT
Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to
any absolute maximum rating for extended periods may affect device performance and reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
RELIABILITY CHARACTERISTICS
Min
0°C
-40°C
Max
+70°C
+85°C
2012 PGM T7 1.0
Symbol
Parameter
Min. Max.
Units
Reference Test Method
NEND(3) Endurance
100,000
Cycles/Byte MIL-STD-883, Test Method 1033
TDR(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
VZAP(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-Up
100
mA JEDEC Standard 17
2012 PGM T2 1.1
D.C. OPERATING CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Limits
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
ICC Power Supply Current
(Operating)
3 mA DI = 0.0V, fSK = 1MHz
VCC = 5.0V, CS = 5.0V,
Output Open
ISB Power Supply Current
(Standby)
50 µA CS = 0V
Reset Outputs Open
ILI Input Leakage Current
ILO Output Leakage Current
(Including ORG pin)
2 µA VIN = 0V to VCC
10 µA VOUT = 0V to VCC,
CS = 0V
VIL1 Input Low Voltage
VIH1 Input High Voltage
-0.1
2
0.8
VCC+1
V 4.5V-VCC<5.5V
V
VIL2 Input Low Voltage
VIH2 Input High Voltage
0
VCC × 0.7
VCC × 0.2
VCC+1
V 1.8V-VCC<2.7V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.4
0.4 V 4.5V-VCC<5.5V
V IOL = 2.1mA
IOH = -400µA
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC-0.2
0.2 V 1.8V-VCC<2.7V
V IOL = 1mA
IOH = -100µA
2012 PGM T3 1.1
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
2012 2.0 4/18/00
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관련 데이터시트

부품번호상세설명 및 기능제조사
S93662

Voltage Monitor and Reset Controller

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S93663

Voltage Monitor and Reset Controller

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