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SA555D 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 SA555D은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 SA555D 기능
기능 Single Timer
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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SA555D 데이터시트, 핀배열, 회로
LM555/NE555/SA555
Single Timer
www.fairchildsemi.com
Features
• High Current Drive Capability (200mA)
• Adjustable Duty Cycle
• Temperature Stability of 0.005%/°C
• Timing From µSec to Hours
• Turn off Time Less Than 2µSec
Applications
• Precision Timing
• Pulse Generation
• Time Delay Generation
• Sequential Timing
Description
The LM555/NE555/SA555 is a highly stable controller
capable of producing accurate timing pulses. With a
monostable operation, the time delay is controlled by one
external resistor and one capacitor. With an astable
operation, the frequency and duty cycle are accurately
controlled by two external resistors and one capacitor.
8-DIP
1
8-SOP
1
Internal Block Diagram
GND 1
R
Trigger 2
Comp.
RR
8 Vcc
Discharging Tr.
7 Discharge
Output 3
OutPut
Stage
F/F
Reset 4
Vref
Comp.
6 Threshold
Control
5
Voltage
©2002 Fairchild Semiconductor Corporation
Rev. 1.0.3




SA555D pdf, 반도체, 판매, 대치품
LM555/NE555/SA555
Application Information
Table 1 below is the basic operating table of 555 timer:
Table 1. Basic Operating Table
Threshold Voltage
(Vth)(PIN 6)
Trigger Voltage
(Vtr)(PIN 2)
Reset(PIN 4) Output(PIN 3)
Discharging Tr.
(PIN 7)
Don't care
Don't care
Low Low
ON
Vth > 2Vcc / 3
Vth > 2Vcc / 3
High
Low
ON
Vcc / 3 < Vth < 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3
High
-
-
Vth < Vcc / 3
Vth < Vcc / 3
High
High
OFF
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or
the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to
threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr.
turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained
low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal
discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
1. Monostable Operation
Trigger
RL
4
RESET
2 TRIG
8
Vcc
DISCH 7
THRES 6
3 OUT
GND
1
CONT 5
+Vcc
RA
C1
C2
Figure 1. Monoatable Circuit
102
101
100
10-1
10-2
10-3
10-5 10-4 10-3 10-2 10-1 100 101 102
Time Delay(s)
Figure 2. Resistance and Capacitance vs.
Time delay(td)
Figure 3. Waveforms of Monostable Operation
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SA555D 전자부품, 판매, 대치품
VC1(t)
=
23-- VCC
=
VCC
1
2--
3
-
e
(---R-----A-----+---t--HR----B-----)--C-----1--

tH = C1(RA + RB)In2 = 0.693(RA + RB)C1
(4)
(5)
The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:
RB
C1 VC1(0-)=2Vcc/3
RD
LM555/NE555/SA555
C1
d----v---C-----1--
dt
+
-----------1-----------
RA + RB
VC1
=
0
(6)
VC1(t)
=
2--
3
V
C
Ce
-
------------------t------------------
(RA + RD)C1
(7)
Since the duration of the timer output low state(tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,
1--
3
VC
C
=
2--
3
VCCe
-
----------------t--L------------------
(RA + RD)C1
(8)
tL = C1(RB + RD)In2 = 0.693(RB + RD)C1
(9)
Since RD is normally RB>>RD although related to the size of discharging Tr.,
tL=0.693RBC1
(10)
Consequently, if the timer operates in astable, the period is the same with
'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge
time. And since frequency is the reciprocal of the period, the following applies.
frequency,
f
=
-1--
T
=
(---R-----A-----+--1---2.--4--R-4---B-----)--C-----1-
(11)
3. Frequency divider
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure
8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.
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