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SE5537 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 SE5537
기능 Sample-and-hold amplifier
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SE5537 데이터시트, 핀배열, 회로
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2kload. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
FEATURES
Operates from ±5V to ±18V supplies
Hold leakage current 6pA @ TJ = 25°C
Less than 4µs acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01µF
Low input offset: 1MV (typical)
0.002% gain accuracy with RL=2k
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
PIN CONFIGURATIONS
FE and N Packages
V+ 1
OFFSET ADJUST 2
INPUT 3
V– 4
8 LOGIC
7 LOGIC REFERENCE
6 Ch
5 OUTPUT
D1 Package
INPUT 1
NC 2
V– 3
NC 4
NC 5
NC 6
OUTPUT 7
14 VOS ADJ
13 NC
12 V+
11 LOGIC
10 LOGIC REFERENCE
9 NC
8 Ch
NOTE:
1. SO and non-standard pinouts.
BLOCK DIAGRAM
OFFSET
2
3
INPUT
LOGIC 8
7
LOGIC
REFERENCE
+
+
30k
5
OUTPUT
300
6
HOLD
CAPACITOR
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-55°C to +125°C
ORDER CODE
NE5537N
NE5537D
SE5537FE
DWG #
0404B
0175D
0404B
August 31, 1994
884 853-1044 13721




SE5537 pdf, 반도체, 판매, 대치품
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current
25
20
15
10
5
0
–5
–10
–15
–50 –25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
Output Short-Circuit Current
30
28
26
24 SOURCING
22
20
SINKING
18
16
14
12
10
–50 –25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
Gain Error
1
0.8 TJ = 25°C
0.6
RL = 2k
SAMPLE MODE
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–15 –10
–5
0
5
INPUT VOLTAGE (V)
10 15
Hold Step
Leakage Current Into
Hold Capacitor
100 10
V+ = V– = 15V
VS = ±15V
TJ = 25°C
VOUT = 0
10 1 HOLD MODE
1 10–1
0.1 10–2
0.01
100pF 1000pF
0.01µF
0.1µF
HOLD CAPACITOR
1µF
10–3
–50 –25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
Hold Step vs Input Voltage
2
1.8
1.6
1.4 TJ = 100°C
1.2
1 TJ = 25°C
0.8
0.6
0.4 TJ = –55°C
0.2
0
–15 –10 –5 0 5
10 15
INPUT VOLTAGE (V)
Acquisition Time
1
VIN = 0 TO ±10V
TJ = 25°C
1%
10
0.1%
0.01%
100
1000
0.001
0.01
HOLD CAPACITOR (µF)
0.1
Aperture Time
250
225 V+ = V– = 15V
VOUT 1mV
200
175
NEGATIVE
150
INPUT
STEP
125
VIN – 10V
100
75
50
POSITIVE
INPUT
25 STEP
0
–50 –25 0
25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
Capacitor Hysteresis
100 MYLAR
HYSTERESIS
POLYPROPYLENE
AND POLYSTYRENE
TIME CONSTANT
10
1
MYLAR
TIME
CONSTANT
0.1
0.1
1
POLYPROPYLENE
AND POLYSTYRENE
HYSTERSIS
10 100
SAMPLE TIME (ms)
August 31, 1994
887

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SE5537 전자부품, 판매, 대치품
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
3
ANALOG INPUT
SAMPLE 5V
HOLD 0V
LOGIC
INPUT
V+
1 V–
4
5
6
OUTPUT
7
8
Ch
Figure 1. Typical Connection
The switch mechanism is on (sampling an information stream) when
the logic level is high (Pin 8 is 1.4V higher than Pin 7) and presents
a load of 5µA to the input logic signal. The analog sampled signal is
amplified, stored (in the external holding capacitor), and buffered. At
the end of the sampling period, the internal switch mechanism turns
off (switch opens) and the “stored analog memory” information on
the external capacitor (Pin 6) is loaded down by an operational
amplifier connected in the unity gain non-inverting configuration.
This input impedance of this amplifier is effectively:
R = RIN (AOL) / (1 + 1/A)
where R = Effective input impedance
RIN = Open-loop input impedance
AOL = Open-loop gain
A = AC loop gain
Therefore, the higher the open-loop gain of the second operational
amplifier, the larger the effective loading on the capacitor. The larger
the load, the lower the “leakage” current and the better the droop
characteristics.
In actuality, the amplifiers are designed with special leakage current
cancellation circuits along with FET input devices. The leakage
current cancellation circuits give better high temperature operation.
(Remember that the FET amplifiers double in required bias current
for every 10 degree increase in junction temperature.)
Sampling time for the NE5537 is less than 10µs (measured to 0.1%
of input signal). Leakage current is 6pA at a rate output load of 2k.
BASIC APPLICATIONS
Multiplying DAC
As depicted in the block diagram of Figure 2, the sample-and-hold
circuit is used to supply a “variable” reference to the digital-to-analog
converter. As the input reference varies, the output will change in
accordance with Equation 1, shown in Figure 2.
Varying the input signal reference level can aid the system in
performing both compression and expansion operations. The
multiplying DACs used are the Philips Semiconductors NE/SE5008;
however, if the rate of change of the reference variation is kept slow
enough, a microprocessor-compatible DAC can be incorporated,
such as the NE5018 or the NE5020.
DATA ACQUISITION SYSTEMS
As mentioned earlier, the designer may wish to operate on several
different segments of an “analog” signal; however, he is limited by
the fact that only one analog-to-digital converter channel is available
to him. Figure 3 shows the means by which a multiplexing system
may be accomplished.
APPLICATION HINTS
Hold Capacitor
A significant source of error in an accurate sample-and-hold circuit
is dielectric absorption in the hold capacitor. A mylar cap, for
instance, may “sag back” up to 0.2% after a quick change in voltage.
A long “soak” time is required before the circuit can be put back in
the hold mode with this type of capacitor. Dielectrics with very low
hysteresis are polystyrene, polypropylene, and teflon. Other types
such as mica and polycarbonate are not nearly as good. Ceramic is
unusable with >1% hysteresis. The advantage of polypropylene over
polystyrene is that it extends the maximum ambient temperature
from 85°C to 100°C. The hysteresis relaxation time constant in
polystyrene, for instance, is 10-50ms. If A-to-D conversion can be
made within 1ms, hysteresis error will be reduced by a factor of ten.
DC ZEROING
DC zeroing is accomplished by connecting the offset adjust pin to
the wiper of a 1kpotentiometer which has one end tied to V+ and
the other end tied through a resistor to ground. The resistor should
be selected to give 0.6mA through the 1kpotentiometer.
Sampling Dynamic Signals
Sampling errors due to moving (changing) input signals are of
significant concern to designers employing sample-and-hold circuits.
There exist finite phase delays through the sample-and-hold circuit
causing an input-output phase of differential for moving signals. In
addition, the series protection resistor (300to Pin 6 of the NE5537)
will add an RC time constant, over and above the slew rate limitation
of the input buffer/current drive amplifier. This means that at the
moment the “HOLD” command arrives, the hold capacitor voltage
may be somewhat different from the actual analog input. The effect
of these delays is opposite to the effect created by delays in the
logic which switches the circuit from sample to hold. For example,
consider an analog input of 20 VP-P at 10kHz. Maximum dV/dt is
0.6V/µs. With no analog phase delay and 100ns logic delay, one
could expect up to (0.1µs) (0.6V/µs) =60mV error if the “HOLD”
signal arrived near maximum dV/dt of the input. A positive-going
input would give a ±60mV error. Now assume a 1MHz (3dB)
bandwidth for the overall analog loop. This generates a phase delay
of 160ns. If the hold capacitor sees this exact delay, then error due
to analog delay will be (0.16µs) (0.6V/µs)=-96mV (analog) for a total
of -36mV. To add to the confusion, analog delay is proportional to
hold capacitor value, while digital delay remains constant. A family
of curves (dynamic sampling error) is included to help estimate
errors.
August 31, 1994
890

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