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PDF LTC1343CGW Data sheet ( Hoja de datos )
| Número de pieza | LTC1343CGW | |
| Descripción | Software-Selectable Multiprotocol Transceiver | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Software-Selectable Transceiver Supports:
RS232, RS449, EIA-530, EIA-530-A, V.35, V.36,
X.21
s NET1 and NET2 Compliant
s Software-Selectable Cable Termination Using
the LTC1344
s 4-Driver/4-Receiver Configuration Provides a
Complete 2-Chip DTE or DCE Port
s Operates from Single 5V Supply
s Internal Echoed Clock and Loop-Back Logic
U
APPLICATIO S
s Data Networking
s CSU and DSU
s Data Routers
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1343
Software-Selectable
Multiprotocol Transceiver
DESCRIPTIO
The LTC®1343 is a 4-driver/4-receiver multiprotocol trans-
ceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or DCE
interface port that supports the RS232, RS449, EIA-530,
EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination
may be implemented using the LTC1344 software-selectable
cable termination chip or by using existing discrete designs.
The LTC1343 runs from a single 5V supply using an internal
charge pump that requires only five space saving surface mount
capacitors. The mode pins are latched internally to allow sharing
of the select lines between multiple interface ports.
Software-selectable echoed clock and loop-back modes help
eliminate the need for external glue logic between the serial
controller and line transceiver. The part features a flow-
through architecture to simplify EMI shielding and is available
in the 44-lead SSOP surface mount package.
TYPICAL APPLICATIO
CTS DSR DCD
DTE Multiprotocol Serial Interface with DB-25 Connector
DTR RTS RL
TM RXD RXC TXC
SCTE TXD LL
LTC1343
R4 R3 R2 R1
D4 D3 D2 D1
LTC1343
R4 R3 R2 R1
D4 D3 D2 D1
LTC1344
13 5 22 6 10 8
23 20 19 4 21 1 7 25 16 3 9 17 12 15
11 24 14 2 18
DB-25 CONNECTOR
1343 TA01
1
1 page  
LTC1343
ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX
V.10 Receiver
VTH Receiver Input Threshold Voltage
∆VTH
IIN
RIN
tr, tf
t PLH
tPHL
V.28 Driver
Receiver Input Hysteresis
Receiver Input Current
Receiver Input Impedance
Rise or Fall Time
Input to Output
Input to Output
0°C ≤ TA ≤ 70°C
–7V ≤ VCM ≤ 7V, – 40°C ≤ TA ≤ 85°C
– 10V ≤ VA ≤ 10V
– 10V ≤ VA ≤ 10V
(Figures 5, 9)
(Figures 5, 9)
(Figures 5, 9)
q – 0.2
q – 0.3
q
q
q 20
0.2
0.3
11 50
±0.50
30
15
350
350
VO Output Voltage
ISS Short-Circuit Current
IOZ Output Leakage Current
Open Circuit
RL = 3k (Figure 4)
VO = GND
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
q ±5
q
q
7.6
±0.01
± 10
± 150
± 100
SR Slew Rate
tPLH Input to Output
tPHL Input to Output
V.28 Receiver
(Figures 4, 8), RL = 3k, CL = 2500pF
(Figures 4, 8), RL = 3k, CL = 2500pF
(Figures 4, 8), RL = 3k, CL = 2500pF
q 4.0
q
q
30.0
1.6 2.5
1.6 2.5
VTHL
VTLH
∆VTH
RIN
tr, tf
tPLH
tPHL
Input Low Threshold Voltage
Input High Threshold Voltage
Receiver Input Hysteresis
Receiver Input Impedance
Rise or Fall Time
Input to Output
Input to Output
– 15V ≤ VA ≤ 15V
(Figures 5, 9)
(Figures 5, 9), CTRL = 0V
CTRL = VCC
(Figures 5, 9), CTRL = 0V
CTRL = VCC
q 1.4 0.8
q 2.0
1.4
q 0.1 0.4 1.0
q3 5 7
15
110
q 330 800
170
q 480 800
UNITS
V
V
mV
mA
kΩ
ns
ns
ns
V
V
mA
µA
V/µs
µs
µs
V
V
V
kΩ
ns
ns
ns
ns
ns
Note 1: Absolute Maximum Ratings are those beyond which the safety of a
device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for VCC = 5V, C1 = C2 = CVCC = CVDD = 1µF,
CVEE = 3.3µF tantalum capacitors and TA = 25°C.
PIN FUNCTIONS
VDD (Pin 1): Generated Positive Supply Voltage for
RS232. Connect a 1µF capacitor to ground.
C1+ (Pin 2): Capacitor C1 Positive Terminal. Connect a
1µF capacitor between C1+ and C1 –.
PWRVCC (Pin 3): Positive Supply for the Charge Pump.
4.75V ≤ PWRVCC ≤ 5.25V. Tie to VCC (Pin 8) and bypass
with a 1µF capacitor to ground.
C1–␣ (Pin 4): Capacitor C1 Negative Terminal.
D1 (Pin 5): TTL Level Driver 1 Input.
D2 (Pin 6): TTL Level Driver 2 Input.
D3 (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS
level output when the chip is in the echoed clock mode
(EC = 0V).
5
5 Page 
LTC1343
APPLICATIONS INFORMATION
PORT #1
M0
M1
M2
DCE/DTE
LATCH
PORT #2
M0
M1
M2
DCE/DTE
CONTROLLER
M0
M1
M2
DCE/DTE
LATCH 1
LATCH 2
LATCH 3
LATCH
PORT #3
M0
M1
M2
DCE/DTE
LATCH
Figure 12: Mode Selection by the Controller
1343 F12
has a unique data latch signal which acts as a write enable.
When the LATCH pin is low the buffers on the M0, M1, M2,
CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high the buffers latch the
data and changes on the input pins will no longer affect
the chip.
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VCC.
Cable Termination
Traditional implementations have included switching re-
sistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head, or separate termi-
nations are built on the board and a custom cable routes
the signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
Using the LTC1344 along with the LTC1343 solves the
cable termination switching problem. Via software con-
trol, the LTC1344 provides termination for the V.10
(RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical
protocols.
V.10 (RS423) Interface
A typical V.10 unbalanced interface is shown in Figure 13.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' con-
nected to A, and input B' connected to the signal return
ground C. The receiver’s ground C' is separate from the
signal return. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 14.
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
A A'
C B'
C'
Figure 13. Typical V.10 Interface
IZ
1343 F13
3.25mA
–10V
–3V
3V
VZ
10V
–3.25mA
1343 F14
Figure 14. V.10 Receiver Input Impedance
11
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC1343CGW.PDF ] | |
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