PDF LTC1346A Data sheet ( Hoja de datos )

Número de pieza	LTC1346A
Descripción	10Mbps DCE/DTE V.35 Transceiver
Fabricantes	Linear Technology
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No Preview Available ! FEATURES ■ Single Chip Provides Complete Differential Signal Interface for V.35 Port ■ Drivers and Receivers Will Withstand Repeated ±10kV ESD Pulses ■ Operates from ±5V Supplies ■ 10Mbaud Transmission Rate ■ Meets CCITT V.35 Specification ■ Shutdown Mode Reduces ICC to Below 1µA ■ Selectable Transmitter and Receiver Configurations ■ Independent Driver/Receiver Enables ■ Transmitter Maintains High Impedance When Disabled, Shut Down or with Power Off ■ Transmitters Are Short-Circuit Protected U APPLICATIO S ■ Modems ■ Telecommunications ■ Data Routers LTC1346A 10Mbps DCE/DTE V.35 Transceiver DESCRIPTIO The LTC®1346A is a single chip transceiver that provides the differential clock and data signals for a V.35 interface from ±5V supplies. Combined with an external resistor termination network and an LT®1134A RS232 transceiver for the control signals, the LTC1346A forms a complete low power DTE or DCE V.35 interface port. The LTC1346A features three current output differential transmitters and three differential receivers. The transceiver can be configured for DTE or DCE operation or shutdown using three Select pins. In the Shutdown mode, the supply current is reduced to below 1µA. The LTC1346A transceiver operates up to 10Mbaud. All transmitters feature short-circuit protection. Both the transmitter outputs and the receiver outputs can be forced into a high impedance state. The transmitter outputs and receiver inputs feature ±10kV ESD protection. , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO Clock and Data Signals for V.35 Interface VEE1 –5V + 0.1mF 1 VCC1 5V + 2 0.1mF 4 5 9 10 11 7 8 VCC1 LTC1346A DX DX RX RX RX 12 DTE BI 627T500/1250 24 1 23 2 22 3 T 21 4 18 14 T 17 13 16 12 T 15 11 14 10 T 13 9 T 3 87 TXD (103) SCTE (113) TXC (114) RXC (115) RXD (104) GND (102) DCE BI 627T500/1250 12 16 T 11 15 10 14 T 9 13 1 24 T 2 23 3 22 T 4 21 5 20 T 6 19 87 3 LTC1346A RX 1 2 + VCC2 5V 0.1mF 10 VEE2 0.1mF –5V 11 RX 4 DX 5 DX 6 DX 50W 125W T= 7 VCC2 50W 8 12 BI TECHNOLOGIES 627T500/1250 (SOIC) LTC1346 • TA01 1346afa 1 1 page LTC1346A FU CTIO TABLES Transmitter and Receiver Configuration S0 S1 S2 DX ON RX ON Description 00 0 — 1, 2, 3 All RX ON, All DX OFF 10 0 — — All OFF, Shutdown 0 1 0 1, 2, 3 1, 2 DCE Mode 1 1 0 1, 2, 3 — DCE Mode, All RX OFF 0 0 1 1, 2 1, 2, 3 DTE Mode 1 0 1 1, 2 — DTE Mode, All RX OFF 0 1 1 1, 2, 3 1, 2, 3 All ON 1 1 1 1, 2, 3 — All DX ON, All RX OFF Transmitter INPUTS OUTPUTS CONFIGURATION S0 S1 S2 T Y1 AND Y2 Z1 AND Z2 Y3 Z3 All OFF 000X Z Z ZZ Shutdown 100X Z Z ZZ DCE or All ON X 1 X 0 0 1 01 DCE or All ON X 1 X 1 1 0 10 DTE X010 0 1 ZZ DTE X011 1 0 ZZ Receiver INPUTS CONFIGURATION S0 S1 S2 A – B All Rx ON 0 0 0 ≤ –0.2V All Rx ON 0 0 0 ≥ 0.2V Shutdown 10 0 X DCE 0 1 0 ≤ –0.2V DCE Disabled 01 0 11 0 ≥ 0.2V X DTE or All ON 0 X 1 ≤ –0.2V DTE or All ON 0 X 1 ≥0.2V Disabled 1X 1 X OUTPUTS R1 AND R2 R3 00 11 ZZ 0Z 1Z ZZ 00 11 ZZ TEST CIRCUITS Y 50Ω T Y VOD 125Ω VOS 125Ω 50Ω A Z 50Ω B 50Ω VOC = (VY + VZ)/2 R S0 15pF Z LTC1346A • F01 Figure 1. V.35 Transmitter/Receiver Test Circuit VCC RECEIVER OUTPUT 1k CL SW1 SW2 LTC1346A • F02 Figure 2. Receiver Output Enable and Disable Timing Test Load 1346afa 5 5 Page APPLICATIONS INFORMATION LTC1346A LOGIC INPUT LT1030 LTC487 LTC1346A V.35 DIFFERENTIAL CONNECTION WITH TERMINATION 50Ω 125Ω 50Ω RS422 DIFFERENTIAL CONNECTION Figure 12a. Multiprotocol Transmitter RS232 CONNECTION NO CONNECTION 1346A F12a LOGIC OUTPUT LTC1346A V.35 DIFFERENTIAL CONNECTION WITH TERMINATION RS422 DIFFERENTIAL CONNECTION WITH TERMINATION RS232 CONNECTION WITH TERMINATION 50Ω 125Ω 50Ω 100Ω 5k 1346A F12b Figure 12b. Multiprotocol Receiver Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1346afa 11 11 Page

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