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PDF BS616LV8010 Data sheet ( Hoja de datos )
| Número de pieza | BS616LV8010 | |
| Descripción | Very Low Power/Voltage CMOS SRAM 512K X 16 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Single CE Pin) BS616LV8010
FEATURES
• Vcc operation voltage : 2.7~3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV8010 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.5uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8010 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV8010EC
BS616LV8010FC
BS616LV8010EI
BS616LV8010FI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns : 3.0~3.6V
70ns : 2.7~3.6V
+0 O C to +70OC 2.7V ~ 3.6V 55 / 70
-40 O C to +85OC 2.7V ~ 3.6V 55 / 70
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC , Max )
Vcc=3V
Vcc=3V Vcc=3V
55ns
70ns
5uA 30mA 24mA
10uA
31mA 25mA
PKG TYPE
TSOP2-44
BGA-48-0912
TSOP2-44
BGA-48-0912
PIN CONFIGURATIONS
BLOCK DIAGRAM
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV8010EC
BS616LV8010EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
Vss
Vcc
DQ11
DQ10
DQ9
DQ8
A8
A9
A10
A11
A12
A13
1 2345 6
A LB OE A0 A1 A2 NC
B D8 UB A3 A4 CE D0
C D9 D10 A5 A6 D1 D2
D V SS D11 A17 A7 D3 VCC
E V CC D12 VSS A16 D4 V SS
F D14 D13 A 14 A 15 D5
D6
G D15 N.C A12 A 13 WE D7
H A18 A 8 A9 A10 A 11 NC
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
D0
.
.
.
.
D15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 4096
4096
Column I/O
Write Driver
Sense Amp
256
Column Decoder
CE
WE
OE
UB
LB
Vcc
Vss
Control
16
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8010
1
Revision 1.1
Jan. 2004
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
t RC
CE
LB,UB
D OUT
t ACS
t BA
t (5)
CLZ
t BE
READ CYCLE3 (1,4)
ADDRESS
t RC
t AA
OE
t OE
CE
LB,UB
t OLZ
t ACS
t (5)
CLZ
t BE
t BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL .
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV8010
5
BS616LV8010
t OH
t tBDO
(5)
CHZ
t OH
t (5)
OHZ
t (1,5)
CHZ
t BDO
Revision 1.1
Jan. 2004
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet BS616LV8010.PDF ] | |
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