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PDF IS24C64A Data sheet ( Hoja de datos )
| Número de pieza | IS24C64A | |
| Descripción | 65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM | |
| Fabricantes | Integrated Silicon Solution | |
| Logotipo |  |
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IS24C32A/B
IS24C64A/B
ISSI®
65,536 bit/32,768 bit
2-WIRE SERIAL CMOS EEPROM
ADVANCED INFORMATION
MAY 2004
FEATURES
• Two-Wire Serial Interface
–Bi-directional data transfer protocol
• 400 KHz (I2C Protocol) Compatibility
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Flexible Voltage Operation
–Vcc = 1.8V to 5.5V for –2 version
–Vcc = 2.5V to 5.5V for –3 version
• Hardware Data Protection
–IS24C32A/64A: WP protects entire array
–IS24C32B/64B: WP protects top quarter of
array
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP
packages
• Self time write cycle with auto clear
5 ms @ 2.5V
• Organization:
–IS24C32A/B: 4Kx8 (128 pages of 32 bytes)
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)
• 32 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Commercial and Industrial temperature ranges
DESCRIPTION
The IS24C32A/B and IS24C64A/B are electrically
erasable PROM devices that use the standard 2-
wire interface for communications. The IS24C32A/B
and IS24C64A/B contain a memory array of 32K-
bits (4K x 8) and 64K-bits (8K x 8), respectively.
Each device is organized into 32 byte pages for
page write mode.
This EEPROM is offered in wide operating volt-
ages of 1.8V to 5.5V (IS24Cxx-2) and 2.5V to 5.5V
(IS24Cxx-3) to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution.
The devices are available in 8-pin PDIP, 8-pin
SOIC and 8-pin TSSOP packages.
The IS24C32A/32B/64A/64B (IS24CXX) maintains
compatibility with the popular 2-wire bus protocol,
so it is easy to use in applications implementing
this bus type. The simple bus consists of the
Serial Clock wire (SCL) and the Serial Data wire
(SDA). Using the bus, a Master device such as a
microcontroller is usually connected to one or
more Slave devices such as this device. The bit
stream over the SDA line includes a series of
bytes, which identifies a particular Slave device,
an instruction, an address within that Slave device,
and a series of data, if appropriate. The IS24CXX
has a Write Protect pin (WP) to allow blocking of
any write instruction transmitted over the bus.
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
05/05/04
1
1 page  
IS24C32A/B
IS24C64A/B
ISSI ®
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
is set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
Current Address Read
The IS24CXX contains an internal address counter which
maintains the address of the last byte accessed, incremented
by one. For example, if the previous operation is either a
Read or Write operation addressed to the address location
n, the internal address counter would increment to address
location n+1. When the EEPROM receives the Slave
Addressing Byte with a Read operation (R/W bit set to “1”),
it will respond an ACK and transmit the 8-bit data byte stored
ataddresslocationn+1. TheMastershouldnotacknowledge
the transfer but should generate a Stop condition so the
IS24CXX discontinues transmission. If 'n' is the last byte
of the memory, then the data from location '0' will be
transmitted. (Refer to Figure 8. Current Address Read
Diagram.)
Random Address Read
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read.
After the IS24CXX acknowledges the byte address, the
Master device resends the Start condition and the Slave
address, this time with the R/W bit set to one. The
EEPROM then responds with its ACK and sends the data
requested. The Master device does not send an ACK but
will generate a Stop condition. (Refer to Figure 9. Random
Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
AddressReadorRandomAddressRead. AftertheIS24CXX
sends initial byte sequence, the Master device now responds
with an ACK indicating it requires additional data from the
IS24CXX. The EEPROM continues to output data for each
ACK received. The Master device terminates the sequential
Read operation by pulling SDA High (no ACK) indicating the
last data word to be read, followed by a Stop condition.
The data output is sequential, with the data from address n
followed by the data from address n+1, n+2 ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary of 8191 for IS24C64A/B or 4095 for IS24C32A/B
(depending on the device) is reached, the address counter
“rolls over” to address 0, and the device continues to output
data. (Refer to Figure 10. Sequential Read Diagram).
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
05/05/04
5
5 Page 
IS24C32A/B
IS24C64A/B
ISSI ®
DC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC), Industrial (TA = -40oC to +85oC)
Symbol Parameter
VOL1
Output Low Voltage
VOL2
Output Low Voltage
VIH Input High Voltage
VIL Input Low Voltage
ILI Input Leakage Current
ILO Output Leakage Current
Test Conditions
VCC = 1.8V, IOL = 0.15 mA
VCC = 2.5V, IOL = 3 mA
VIN = VCC max.
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Commercial (TA = 0oC to +70oC), Industrial (TA = -40oC to +85oC)
Symbol Parameter
ICC1 Vcc Operating Current
ICC2 Vcc Operating Current
ISB1 Standby Current
ISB2 Standby Current
ISB3 Standby Current
Test Conditions
Read at 400 KHz (Vcc = 5V)
Write at 400 KHz (Vcc = 5V)
Vcc = 1.8V
Vcc = 2.5V
Vcc = 5.0 V
Min.
Max.
— 0.2
— 0.4
VCC X 0.7 VCC + 0.5
–1.0 VCC X 0.3
—3
—3
Unit
V
V
V
V
µA
µA
Min.
—
—
—
—
—
Max.
2.0
3.0
1
2
6
Unit
mA
mA
µA
µA
µA
AC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC) Industrial (TA = -40oC to +85oC)
Symbol
fSCL
T
tLow
tHigh
tBUF
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tSU:WP
tHD:WP
tDH
tAA
tR
tF
tWR
Parameter
SCL Clock Frequency
Noise Suppression Time(1)
Clock Low Period
Clock High Period
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
Data In Hold Time
WP pin Setup Time
WP pin Hold Time
Data Out Hold Time (SCL Low to SDA Data Out Change)
Clock to Output (SCL Low to SDA Data Out Valid)
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
1.8V-5.5V
Min. Max.
0 100
— 100
4.7 —
4—
4.7 —
4—
4—
4—
4—
100 —
0—
4—
4.7 —
100 —
100 3500
— 1000
— 300
— 10
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
05/05/04
2.5V-5.5V
Min. Max.
0 400
— 50
1.2 —
0.6 —
1.2 —
0.6 —
0.6 —
0.6 —
0.6 —
100 —
0—
0.6 —
1.2 —
50 —
50 900
— 300
— 300
— 10
4.5V-5.5V
Min. Max.
0 1000
— 50
0.6 —
0.4 —
0.5 —
0.25 —
0.25 —
0.25 —
0.25 —
100 —
0—
0.6 —
1.2 —
50 —
50 400
— 300
— 100
—5
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ms
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IS24C64A.PDF ] | |
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