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PDF 27C256 Data sheet ( Hoja de datos )
| Número de pieza | 27C256 | |
| Descripción | 262 /144-Bit (32K x 8) High Performance CMOS EPROM | |
| Fabricantes | National | |
| Logotipo |  |
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1. 27C256  Hay una vista previa y un enlace de descarga de 27C256 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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March 1989
27C256
262 144-Bit (32 768 x 8) UV Erasable CMOS PROM
Military Qualified
General Description
The 27C256 is a high-speed 256K UV erasable and electri-
cally reprogrammable CMOS EPROM ideally suited for ap-
plications where fast turnaround pattern experimentation
and low power consumption are important requirements
The 27C256 is designed to operate with a single a5V pow-
er supply with g10% tolerance The CMOS design allows
the part to operate over Military Temperature Range
The 27C256 is packaged in a 28-pin dual-in-line package
with transparent lid and a 32-pin windowed LCC The trans-
parent lid allows the user to expose the chip to ultraviolet
light to erase the bit pattern A new pattern can then be
written electrically into the device by following the program-
ming procedure
This EPROM is fabricated with National’s proprietary time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability
The 27C256 specified on this data sheet is fully compliant
with MIL-STD-883 Revision C
Features
Y Clocked sense amps for fast access time down to
250 ns
Y Low CMOS power consumption
Active power 55 mW max
Standby power 0 55 mW max
Y Performance compatible to NSC800TM CMOS
microprocessor
Y Single 5V power supply
Y Pin compatible with NMOS 256K EPROMs
Y Fast and reliable programming (0 5 ms for most bytes)
Y Static operation no clocks required
Y TTL CMOS compatible inputs outputs
Y TRI-STATE output
Y Optimum EPROM for total CMOS systems
Y Windowed DIP and LCC package options
Y Specifications guaranteed over full military temperature
range (b55 C to a125 C)
Y This device is processed in compliance with SMD
86063 and the DIP version is dual marked
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
NSC800TM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL D 10332
Pin Names
A0 – A14
CE
OE
O0 – O7
PGM
NC
Addresses
Chip Enable
Output Enable
Outputs
Program
No Connect
TL D 10332 – 1
RRD-B30M105 Printed in U S A
1 page  
Programming Characteristics (Notes 1 2 3 and 4)
Symbol
Parameter
Conditions Min Typ Max Units
tAS
tOES
tVPS
tVCS
tDS
tAH
tDH
tDF
Address Setup Time
OE Setup Time
VPP Setup Time
VCC Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Output Enable to
Output Float Delay
CE e VIL
2
2
2
2
2
0
2
0
ms
ms
ms
ms
ms
ms
ms
130 ns
tPW Program Pulse Width
0 5 0 5 10
ns
tOE Data Valid from OE
CE e VIL
150 ns
IPP VPP Supply Current during
Programming Pulse
CE e VIL
PGM e VIL
30 mA
ICC VCC Supply Current
10 mA
TA Temperature Ambient
20 25 30
C
VCC Power Supply Voltage
5 75 6 0 6 25
V
VPP Programming Supply Voltage
12 2 13 0 13 3
V
tFR Input Rise Fall time
5 ns
VIL Input Low Voltage
0 0 0 45
V
VIH Input High Voltage
24 40
V
tIN Input Timing Reference Voltage
08 15 20
V
tOUT
Output Timing Reference Voltage
08 15 20
V
Note 1 National’s standard product warranty applies only to devices programmed to specifications described herein
Note 2 VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP The EPROM must not be inserted into or removed from a
board with voltage applied to VPP or VCC
Note 3 The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V Care must be taken when switching the VPP
supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 mF capacitor is required across VPP VCC to GND to suppress
spurious voltage transients which may damage the device
Note 4 Programming and program verify are tested with the Interactive Program Algorithm at typical power supply voltages and timings The Min and Max Limit
Parameters are Design parameters not Tested or guaranteed
Programming Waveforms (Note 3)
TL D 10332 – 4
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 27C256.PDF ] | |
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