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27C4100 데이터시트 PDF




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부품번호 27C4100 기능
기능 4M-BIT [512K x 8/256K x 16] CMOS EPROM
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27C4100 데이터시트, 핀배열, 회로
MX27C4100/27C4096
4M-BIT [512K x 8/256K x 16] CMOS EPROM
FEATURES
256K x 16 organization(MX27C4096, JEDEC pin
out)
512K x 8 or 256K x 16 organization(MX27C4100,
ROM pin out compatible)
+12.5V programming voltage
Fast access time: 100/120/150 ns
Totally static operation
Completely TTL compatible
Operating current: 60mA
Standby current: 100uA
Package type:
- 40 pin plastic DIP
- 44 pin PLCC
- 40 pin SOP
GENERAL DESCRIPTION
The MX27C4100/4096 is a 5V only, 4M-bit, One Time
Programmable Read Only Memory. It is organized as
256K words by 16 bits per word(MX27C4096), 512K x 8
or 256K x 16(MX27C4100), operates from a single + 5
volt supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing EPROM
programmers may be used. The MX27C4100/4096
supports a intelligent fast programming algorithm which
can result in programming time of less than two minutes.
This EPROM is packaged in industry standard 40 pin
dual-in-line packages, 40 lead SOP, and 44 lead PLCC
packages.
PIN CONFIGURATIONS
SOP/PDIP(MX27C4100)
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A8
39 A9
38 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE/VPP
30 GND
29 Q15/A-1
28 Q7
27 Q14
26 Q6
25 Q13
24 Q5
23 Q12
22 Q4
21 VCC
BLOCK DIAGRAM (MX27C4100)
CE
OE
BYTE/VPP
CONTROL
LOGIC
OUTPUT
BUFFERS
A0~A17
ADDRESS
INPUTS
.
.
.
.
.
.
.
.
VCC
GND
Y-DECODER
X-DECODER
.
.
.
.
.
.
.
.
Y-SELECT
4M BIT
CELL
MAXTRIX
Q0~Q14
Q15/A-1
P/N: PM0197
REV. 3.4, AUG. 22, 2001
1




27C4100 pdf, 반도체, 판매, 대치품
MX27C4100/27C4096
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C4100/4096
When the MX27C4100/4096 is delivered, or it is
erased, the chip has all 4M bits in the "ONE" or HIGH
state. "ZEROs" are loaded into the MX27C4100/4096
through the procedure of programming.
For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
VCC must be applied simultaneously or before VPP,
and removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 100us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V ± 10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27C4100/4096's in parallel
with different data is also easily accomplished by using
the Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C4100/4096 may be
common. A TTL low-level program pulse applied to an
MX27C4100/4096 CE input with VPP = 12.5 ± 0.5 V will
program the MX27C4100/4096. A high-level CE input
inhibits the other MX27C4100/4096s from being
programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE and CE at
VIL(for MX27C4096), OE at VIL and CE at VIH(for
MX27C4100) and VPP at its programming voltage.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C± 5°C ambient
temperature range that is required when programming
the MX27C4100/4096.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C4100/4096, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
READ MODE
The MX27C4100/4096 has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and
addresses have been stable for at least tACC - t OE.
WORD-WIDE MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
P/N: PM0197
REV. 3.4, AUG. 22, 2001
4

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27C4100 전자부품, 판매, 대치품
MX27C4100/27C4096
FIGURE 1. FAST PROGRAMMING FLOW CHART
INTERACTIVE
SECTION
VERIFY SECTION
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X=0
PROGRAM ONE 100us PULSE
INCREMENT X
X = 25?
YES
FAIL
INCREMENT ADDRESS
NO
NO
VERIFY BYTE
?
PASS
LAST ADDRESS
YES
VCC = VPP = 5.25V
FAIL
VERIFY ALL BYTES
?
PASS
DEVICE PASSED
FAIL
DEVICE FAILED
P/N: PM0197
REV. 3.4, AUG. 22, 2001
7

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27C4100

4M-BIT [512K x 8/256K x 16] CMOS EPROM

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