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28C256 데이터시트 PDF




Catalyst에서 제조한 전자 부품 28C256은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 28C256 자료 제공

부품번호 28C256 기능
기능 32K-Bit Parallel E2PROM
제조업체 Catalyst
로고 Catalyst 로고


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28C256 데이터시트, 핀배열, 회로
CAT28C256
32K-Bit Parallel E2PROM
FEATURES
s Fast Read Access Times: 120/150ns
s Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 150 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
s Hardware and Software Write Protection
s Automatic Page Write Operation:
–1 to 64 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
–DATA Polling
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commerical, Industrial and Automotive
Temperature Ranges
The CAT28C256 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A6–A14
VCC
CE
OE
WE
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0–A5
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25020-0A 2/98




28C256 pdf, 반도체, 판매, 대치품
CAT28C256
MODE SELECTION
Mode
CE WE OE I/O Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H DIN ACTIVE
Byte Write (CE Controlled)
L H DIN ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
CI/O(1)
Input/Output Capacitance
CIN(1)
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
Symbol Parameter
tRC Read Cycle Time
tCE CE Access Time
tAA
tOE
tLZ(1)
tOLZ(1)
tHZ(1)(2)
tOHZ(1)(2)
tOH(1)
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
28C256-12
Min. Max.
120
120
120
50
0
0
50
50
0
28C256-15
Min. Max.
150
150
150
70
0
0
50
50
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 25020-0A 2/98
4

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28C256 전자부품, 판매, 대치품
CAT28C256
Page Write
The page write mode of the CAT28C256 (essentially an
extended BYTE WRITE mode) allows from 1 to 64 bytes
of data to be programmed within a single E2PROM write
cycle. This effectively reduces the byte-write time by a
factor of 64.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A6
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A5
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [CE Controlled]
ADDRESS
CE
OE
WE
tAS tAH
tCW
tOES
tCS
tOEH
tCH
DATA OUT
HIGH-Z
tBLC
tWC
DATA IN
Figure 6. Page Mode Write Cycle
OE
DATA VALID
tDS
tDH
5096 FHD F07
CE
tWP
tBLC
WE
ADDRESS
I/O
BYTE 0 BYTE 1
BYTE 2
BYTE n BYTE n+1
tWC
LAST BYTE
BYTE n+2
5096 FHD F10
7 Doc. No. 25020-0A 2/98

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