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PDF 29F1610A Data sheet ( Hoja de datos )
| Número de pieza | 29F1610A | |
| Descripción | 16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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FEATURES
• 5V ± 10% write and erase
• JEDEC-standard EEPROM commands
• Endurance:100,000 cycles
• Fast access time: 90/100/120ns
• Sector erase architecture
- 16 equal sectors of 128k bytes each
- Sector erase time: 1.3 s typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors
or the whole chip with Erase Suspend capability
- Automatically programs and verifies data at
specified addresses
• Status Register feature for detection of
program or erase cycle completion
• Low VCC write inhibit is equal to or less than 3.2V
• Software and hardware data protection
PRELIMINARY
MX29F1610A
16M-BIT [2M x8/1M x16] CMOS
SINGLE VOLTAGE FLASH EEPROM
• Page program operation
- Internal address and data latches for
128 bytes/64 words per page
- Page programming time: 0.9ms typical
- Byte programming time: 7us in average
• Low power dissipation
- 30mA typical active current
- 1uA typical standby current
• CMOS and TTL compatible inputs and outputs
• Sector Protection
- Hardware method that can protect any combination
of sectors from write or erase operations.
• Deep Power-Down Input
- 1uA ICC typical
• Industry standard surface mount packaging
- 48 lead TSOP, TYPE I
- 44 lead SOP
GENERAL DESCRIPTION
The MX29F1610A is a 16-mega bit Flash memory
organized as either 1M wordx16 or 2M bytex8. The
MX29F1610A includes 16-128KB(131,072) blocks or 16-
64KW(65,536) blocks. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F1610A is packaged
in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and
RY/BY are extra pins compared with 44-pin SOP package.
This is to optimize the products (such as solid-state disk
drives or flash memory cards) control pin budget. All the
above three pins(CE2,RY/BY and PWD) plus one extra
VCC pin are not provided in 44-pin SOP. It is designed to
be reprogrammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F1610A offers access times as fast as
90ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the
MX29F1610A has separate chip enables(CE1 and CE2),
output enable (OE), and write enable (WE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F1610A uses a command register to manage this
functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
To allow for simple in-system reprogrammability, the
MX29F1610A does not require high input voltages for
programming. Five-volt-only commands determine the
operation of the device. Reading data out of the device
is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100,000 cycles. The MXIC's cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1610A uses a 5V ±10% VCC supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
P/N: PM0506
1 REV.1.7,JUN. 15, 2001
1 page  
MX29F1610A
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Notes PWD CE1 CE2 OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1 RY/BY
Read
1,2,7 VIH VIL VIL VIL VIH X X X
DOUT DOUT
DOUT
X
OutputDisable 1,6,7 VIH VIL VIL VIH VIH X X X
HighZ
HighZ
HighZ
X
Standby
1,6,7
VIH VIL VIH
VIH VIL
VIH VIH
X
XXXX
HighZ
HIghZ
HighZ
X
DeepPower-Down 1,3
VIL X X X
XXXX
HighZ
HighZ
HighZ
VOH
ManufacturerID 4,8 VIH VIL VIL VIL VIH VIL VIL VID C2H
00H
0B VOH
Device ID
MX29F1610A
Write
4,8
1,5,6
VIH VIL VIL VIL VIH VIH VIL VID FAH/FBH
VIH VIL VIL VIH VIL X X X
DIN
00H
DIN
0B VOH
DIN X
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Notes PWD CE1 CE2 OE WE A0 A1 A9 Q0-Q7 Q8-Q14 Q15/A-1 RY/BY
Read
1,2,7,9 VIH VIL VIL VIL VIH X X X
OutputDisable 1,6,7 VIH VIL VIL VIH VIH X X X
DOUT
HighZ
HighZ
HIghZ
VIL/VIH
X
X
X
Standby
1,6,7
DeepPower-Down 1,3
ManufacturerID 4,8
Device ID
MX29F1610A
Write
4,8
1,5,6
VIH VIL VIH
VIH VIL
VIH VIH
X
XXXX
HighZ
VIL X X X X X X X
HighZ
VIH VIL VIL VIL VIH VIL VIL VID
C2H
VIH VIL VIL VIL VIH VIH VIL VID FAH/FBH
VIH VIL VIL VIH VIL X X X
DIN
HighZ
HIghZ
HighZ
High Z
HIghZ
XX
X
VIL
VIL
VIL/VIH
VOH
VOH
VOH
X
NOTES :
1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH.
2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH
if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress.
3.PWD at GND ± 0.2V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate
sector addresses provide Sector Protect Code.(Refer to Table 4)
5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through
proper command sequence.
6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not
busy or in erase suspend mode.
7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation.
8. VID = 11.5V- 12.5V.
9. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.
P/N: PM0506
REV.1.7, JUN. 15, 2001
5
5 Page 
MX29F1610A
READ STATUS REGISTER
The MXIC's16 Mbit flash family contains a status register
which may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The status register may be read
at any time by writing the Read Status command to the
CIR. After writing this command, all subsequent read
operations output data from the status register until
another valid command sequence is written to the CIR.
A Read Array command must be written to the CIR to
return to the Read Array mode.
The status register bits are output on DQ2 - DQ7(table 6)
whether the device is in the byte-wide (x8) or word-wide
(x16) mode for the MX29F1610A. In the word-wide mode
the upper byte, DQ(8:15) is set to 00H during a Read
Status command. In the byte-wide mode, DQ(8:14) are
tri-stated and DQ15/A-1 retains the low order address
function. DQ0-DQ1 is set to 0H in either x8 or x16 mode.
It should be noted that the contents of the status register
are latched on the falling edge of OE or CE whichever
occurs last in the read cycle. This prevents possible bus
errors which might occur if the contents of the status
register change while reading the status register. CE or
OE must be toggled with each subsequent status read, or
the completion of a program or erase operation will not be
evident.
The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whether or not the WSM was successful in performing the
desired operation. The WSM sets status bits four through
seven and clears bits six and seven, but cannot clear
status bits four and five. If Erase fail or Program fail status
bit is detected, the Status Register is not cleared until the
Clear Status Register command is written. The
MX29F1610A automatically outputs Status Register data
when read after Chip Erase, Sector Erase, Page Program
or Read Status Command write cycle. The internal state
machine is set for reading array data upon device power-
up, or after deep power-down mode.
CLEAR STATUS REGISTER
The Eraes fail status bit (DQ5) and Program fail status bit
(DQ4) are set by the write state machine, and can only be
reset by the system software. These bits can indicate
various failure conditions(see Table 6). By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several pages or erasing
multiple blocks in squence). The status register may then
be read to determine if an error occurred during that
programming or erasure series. This adds flexibility to the
way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip) erase are attempted. To clear the status register,
the Clear Status Register command is written to the CIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID.
P/N: PM0506
REV.1.7, JUN. 15, 2001
11
11 Page | ||
| Páginas | Total 39 Páginas | |
| PDF Descargar | [ Datasheet 29F1610A.PDF ] | |
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