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29F800 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 29F800은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 29F800 기능
기능 8 Mbit 1Mb x8 or 512Kb x16 / Boot Block Single Supply Flash Memory
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


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29F800 데이터시트, 핀배열, 회로
M29F800AT
M29F800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
s SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 70ns
s PROGRAMMING TIME
– 8µs per Byte/Word typical
s 19 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 16 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s TEMPORARY BLOCK UNPROTECTION
MODE
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– M29F800AT Device Code: 00ECh
– M29F800AB Device Code: 0058h
TSOP48 (N)
12 x 20mm
44
1
SO44 (M)
Figure 1. Logic Diagram
VCC
19
A0-A18
15
DQ0-DQ14
W DQ15A–1
M29F800AT
E M29F800AB BYTE
G RB
RP
VSS
AI02198B
January 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21




29F800 pdf, 반도체, 판매, 대치품
M29F800AT, M29F800AB
Table 3A. M29F800AT Block Addresses
Size
Address Range
(Kbytes)
(x8)
Address Range
(x16)
16
FC000h-FFFFF h
7E000h-7FFFFh
8
FA000h-FBFFFh
7D000h-7DFFFh
8
F8000h-F9FFFh
7C000h-7CFFFh
32
F0000h-F7FFFh
78000h-7BFFFh
64
E0000h-EFFFF h
70000h-77FFFh
64
D0000h-DFFFFh
68000h-6FFFFh
64
C0000h-CFFFFh
60000h-67FFFh
64
B0000h-BFFFF h
58000h-5FFFFh
64
A0000h-AFFFF h
50000h-57FFFh
64
90000h-9FFFFh
48000h-4FFFFh
64
80000h-8FFFFh
40000h-47FFFh
64
70000h-7FFFFh
38000h-3FFFFh
64
60000h-6FFFFh
30000h-37FFFh
64
50000h-5FFFFh
28000h-2FFFFh
64
40000h-4FFFFh
20000h-27FFFh
64
30000h-3FFFFh
18000h-1FFFFh
64
20000h-2FFFFh
10000h-17FFFh
64
10000h-1FFFFh
08000h-0FFFFh
64
00000h-0FFFFh
00000h-07FFFh
Table 3B. M29F800AB Block Addresses
Size
Address Range
(Kbytes)
(x8)
Address Range
(x16)
64
F0000h-FFFFF h
78000h-7FFFFh
64
E0000h-EFFFFh
70000h-77FFFh
64
D0000h-DFFFF h
68000h-6FFFFh
64
C0000h-CFFFF h
60000h-67FFFh
64
B0000h-BFFFFh
58000h-5FFFFh
64
A0000h-AFFFFh
50000h-57FFFh
64
90000h-9FFFFh
48000h-4FFFFh
64
80000h-8FFFFh
40000h-47FFFh
64
70000h-7FFFFh
38000h-3FFFFh
64
60000h-6FFFFh
30000h-37FFFh
64
50000h-5FFFFh
28000h-2FFFFh
64
40000h-4FFFFh
20000h-27FFFh
64
30000h-3FFFFh
18000h-1FFFFh
64
20000h-2FFFFh
10000h-17FFFh
64
10000h-1FFFFh
08000h-0FFFFh
32
08000h-0FFFFh
04000h-07FFFh
8
06000h-07FFFh
03000h-03FFFh
8
04000h-05FFFh
02000h-02FFFh
16
00000h-03FFFh
00000h-01FFFh
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 14 and Figure 10, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VID will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14 and Figure
10, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The Byte/
Word Organization Select pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When Byte/Word Organization Select is Low,
VIL, the memory is in 8-bit mode, when it is High,
VIH, the memory is in 16-bit mode.
4/21

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29F800 전자부품, 판매, 대치품
M29F800AT, M29F800AB
Table 5A. Commands, 16-bit mode, BYTE = VIH
Bus Write Operations
Command
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1 X F0
3 555 AA 2AA 55 X F0
Auto Select
3 555 AA 2AA 55 555 90
Program
4 555 AA 2AA 55 555 A0 PA PD
Chip Erase
6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase
6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend
1 X B0
Erase Resume
1 X 30
Table 5B. Commands, 8-bit mode, BYTE = VIL
Bus Write Operations
Command
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1 X F0
3 AAA AA 555 55 X F0
Auto Select
3 AAA AA 555 55 AAA 90
Program
4 AAA AA 555 55 AAA A0 PA PD
Chip Erase
6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase
6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend
1 X B0
Erase Resume
1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the
memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until the Timeout
Bit is set.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so will
cause an error. One of the Erase Commands must
be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
7/21

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