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부품번호 | 2K30A 기능 |
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기능 | DSP56301 Digital Signal Processor | ||
제조업체 | Motorola Semiconductors | ||
로고 | |||
전체 21 페이지수
Freescale Semiconductor, Inc.
Chip Errata
DSP56301 Digital Signal Processor
Mask: 2K30A
General remark: In order to prevent the use of instructions or sequences of instructions that
do not operate correctly, we encourage you to use the “lint563” program to identify such
cases and use alternative sequences of instructions. This program is available as part of the
Motorola DSP Tools CLAS package.
Silicon Errata
Errata
Number
Errata Description
Description (added 8/16/2001):
Applies
to Mask
2K30A
ES133
Some K30A devices shipped under an XC part number are subject to a problem
if operated in DMA mode 5. The problem occurs if two consecutive host
commands are sent to the DSP. The second host command is received, the
corresponding answer message is composed, and the DMA channel is set up
correctly to transmit the message to the host. However, the message is never sent.
The host port status register shows a host transmit data request (bit HTRQ in
HSTR is set.) DTDn is never set, indicating there has been no terminated
transfer. Sequences of: 1. data, 2. host command to terminate the transfer, and
3. acknowledgement from the host work properly and can be repeated as often
as needed. If a second host command is sent to the DSP, without first sending
data, the DMA channel locks up. This problem has proven to be low level to
date, occurring at a rate of about 350 ppm. The product’s performance regarding
this issue does not drift over time; that is, it is not a reliability risk.
The problem can also be manifested in other modes when more than one DMA
channel is operating, with two or more channels moving data while one is
servicing the PCI FIFO. In this case, the channel servicing the PCI FIFO stalls
and the PCI bus enters an endless state of retries.
Motorola Semiconductor Products Sector
301CE2K30A_0_8
6501 William Cannon Drive WeFsot,rAMusotirne, TIenxfaosrm7a87ti3o5n-8O59n8 This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 1
1996-2002 Motorola
Errata
Number
ED9
ED10
ED12
Freescale Semiconductor, Inc.
Chip Errata
DSP56301 Digital Signal Processor
Mask:2K30A
Document Update
Applies
to Mask
Description (added 1/27/98):
2K30A
When the SCI is configured in Synchronous mode, internal clock, and all
the SCI pins are enabled simultaneously, an extra pulse of 1 DSP clock
length is provided on the SCLK pin.
Workaround:
a. Enable an SCI pin other than SCLK.
b. In the next instruction, enable the remaining SCI pins, including the
SCLK pin.
Pertains to: UM, SCI Chapter (Use the 302 UM as your reference,
Section 8.4.2, “SCI Initialization”)
Description (added 5/13/98):
2K30A
The HI32 may operate improperly in PCI mode when the TWSD bit
is set in the HCTR register.
Workaround:
Do not set the TWSD bit in the HCTR register; this bit is reserved.
This is a documentation change.
Description (added 5/13/98):
2K30A
When the HI32 is in PCI mode, the HTF control bits affect the
address insertion (the IAE bit is set in the DPCR register) in the
same way they affect the transferred data.
Address as appears on the PCI bus: $12345678
HTF[1:0]
Inserted Address
00 $005678, $001234
01 $345678
10 $345678
11 $123456
Workaround:
This is a documentation update.
DSP56301 Errata
1996-2002, Motorola
For Mor3e01ICnEfo2rKm30aAti_o0n_8On This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 4
4페이지 Errata
Number
ED25
Freescale Semiconductor, Inc.
Chip Errata
DSP56301 Digital Signal Processor
Mask:2K30A
Document Update
Applies
to Mask
Description (added 12/16/98):
2K30A
Current definition:
HDTC is set if SRRQ and MRRQ are cleared (i.e. the host-to-DSP
data path is emptied by DSP56300 core reads) under one of the
following conditions:
• a non-exclusive PCI write transaction to the HTXR termi-
nates or completes
• HLOCK is negated after the completion of an exclusive
write access to the HTXR
• the HI32 initiates a read transaction. The HI32 disconnects
(retry or disconnect-C) forthcoming write accesses to the
HTXR as long as HDTC is set.
New definition:
HDTC is set if SRRQ and MRRQ are cleared (i.e. the host-to-DSP
data path is emptied by DSP56300 Core reads) under one of the
following conditions:
• a non-exclusive PCI write transaction to the HTXR termi-
nates or completes
• HLOCK is negated after the completion of an exclusive
write access to the HTXR. The HI32 disconnects (retry or
disconnect-C) forthcoming write accesses to the HTXR as
long as HDTC is set.
Note: The HDTC bit is not set after a read transaction initiated by
the HI32 as a PCI master.
Workaround:
NTR
DSP56301 Errata
1996-2002, Motorola
For Mor3e01ICnEfo2rKm30aAti_o0n_8On This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 7
7페이지 | |||
구 성 | 총 21 페이지수 | ||
다운로드 | [ 2K30A.PDF 데이터시트 ] |
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2K30 | TVS Diode (Transient Voltage Suppressor) | Microsemi |
2K30A | DSP56301 Digital Signal Processor | Motorola Semiconductors |
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