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PDF 74F192PC Data sheet ( Hoja de datos )
| Número de pieza | 74F192PC | |
| Descripción | Up/Down Decade Counter with Separate Up/Down Clocks | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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April 1988
Revised March 1999
74F192
Up/Down Decade Counter with Separate Up/Down
Clocks
General Description
The 74F192 is an up/down BCD decade (8421) counter.
Separate Count Up and Count Down Clocks are used, and
in either counting mode the circuits operate synchronously.
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down
outputs are used as the clocks for a subsequent stage
without extra logic, thus simplifying multistage counter
designs. Individual preset inputs allow the circuit to be used
as a programmable counter. Both the Parallel Load (PL)
and the Master Reset (MR) inputs asynchronously override
the clocks.
Features
s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74F192SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F192PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009496.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay CPU or
CPD to TCU or TCD
Propagation Delay
CPU or CPD to Qn
Propagation Delay
Pn to Qn
Propagation Delay
PL to Qn
Propagation Delay
MR to Qn
Propagation Delay
MR to TCU
Propagation Delay
MR to TCD
Propagation Delay
PL to TCU or TCD
Propagation Delay
Pn to TCU or TCD
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
100 125
4.0 7.0 9.0
3.5 6.0 8.0
4.0 6.5 8.5
5.5 9.5 12.5
3.0 4.5 7.0
6.0 11.0 14.5
5.0 8.5 11.0
5.5
10.0
13.0
6.5 11.0 14.5
TA = −55°C to +125°C
CL = 50 pF
TA = 0°C to +70°C
CL = 50 pF
Min Max Min Max
75 90
4.0 10.5 4.0 10.0
3.5 9.5 3.5 9.0
4.0 10.0 4.0
9.5
5.5 14.0 5.5 13.5
3.0 8.5 3.0 8.0
6.0 16.5 6.0 15.5
5.0 13.5 5.0 12.0
5.5 15.0 5.5 14.0
6.5 16.0 6.5 15.5
6.0
10.5
13.5
6.0
15.0
6.0
14.5
7.0 11.5 14.5 7.0 16.0 7.0 15.5
7.0
12.0
15.5
7.0
18.5
7.0
16.5
7.0 11.5 14.5 7.0 17.5 7.0 15.5
7.0 11.5 14.5 7.0 16.5 7.0 15.5
6.5 11.0 14.0 6.5 16.5 6.5 15.0
AC Operating Requirements
Symbol
Parameter
tS(H)
tS(L)
tH(H)
tH(L)
tW(L)
tW(L)
tW(L)
tW(H)
tREC
tREC
Setup Time, HIGH or LOW
Pn to PL
Hold Time, HIGH or LOW
Pn to PL
PL Pulse Width, LOW
CPU or CPD
Pulse Width, LOW
CPU or CPD
Pulse Width, LOW
(Change of Direction)
MR Pulse Width, HIGH
Recovery Time
PL to CPU or CPD
Recovery Time
MR to CPU or CPD
TA = +25°C
VCC = +5.0V
Min Max
4.5
4.5
2.0
2.0
6.0
5.0
TA = −55°C to +125°C
TA = 0°C to +70°C
Min Max Min Max
6.0 5.0
6.0 5.0
2.0 2.0
2.0 2.0
7.5 6.0
7.0 5.0
10.0 12.0 10.0
6.0 6.0 6.0
6.0 8.0 6.0
4.0 4.5 4.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74F192PC.PDF ] | |
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