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74F402 데이터시트 PDF




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부품번호 74F402 기능
기능 Serial Data Polynomial Generator/Checker
제조업체 National
로고 National 로고


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74F402 데이터시트, 핀배열, 회로
www.DataSheet4U.com
January 1995
54F 74F402 Serial Data Polynomial
Generator Checker
General Description
The ’F402 expandable Serial Data Polynomial generator
checker is an expandable version of the ’F401 It provides
an advanced tool for the implementation of the most widely
used error detection scheme in serial digital handling sys-
tems A 4-bit control input selects one-of-six generator poly-
nomials The list of polynomials includes CRC-16 CRC-
CCITT and Ethernet as well as three other standard poly-
nomials (56th order 48th order 32nd order) Individual clear
and preset inputs are provided for floppy disk and other
applications The Error output indicates whether or not a
transmission error has occurred The CWG Control input
inhibits feedback during check word transmission The
’F402 is compatible with FAST devices and with all TTL
families
Features
Y Guaranteed 30 MHz data rate
Y Six selectable polynomials
Y Other polynomials available
Y Separate preset and clear controls
Y Expandable
Y Automatic right justification
Y Error output open collector
Y Typical applications
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
Commercial
Military
Package
Number
Package Description
74F402PC
N16E
16-Lead (0 300 Wide) Molded Dual-In-Line
54F402DM (Note 1)
J16A
16-Lead Ceramic Dual-In-Line
54F402FM (Note 1)
W16A
16-Lead Cerpack
54F402LM (Note 1)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9535–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
Ethernet is a registered trademark of Xerox Corporation
C1995 National Semiconductor Corporation TL F 9535
TL F 9535 – 1
TL F 9535 – 2
RRD-B30M105 Printed in U S A




74F402 pdf, 반도체, 판매, 대치품
TABLE II
Select Code P3 P2 P1 P0 C2 C1 C0 Polynomial
0 0 0 0 0 1 0 0 Se0
C 1 1 1 1 1 0 1 Ethernet
D 1 1 1 1 1 0 1 Polynomial
E 0 0 0 0 0 0 0 Ethernet
F 0 0 0 0 0 1 0 Residue
7 1 1 1 1 1 0 0 CRC-16
B 1 1 1 1 1 0 0 CRC-CCITT
3 1111100
2 1 1 1 1 1 0 0 56th
4 1 1 1 1 1 0 0 Order
8 0011100
5 1111100
9
1
1
1
1
1
0
0
48th
Order
1 1111100
6 1 1 1 1 1 0 0 32nd
A 1 1 1 1 1 0 0 Order
Applications
In addition to polynomial selection there are four other ca-
pabilities provided for in the ’F402 ROM The first is set or
clear selectability The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW This set or clear capability is done in four groups of 4
(see Table II P0 – P3) The second ROM capability (C0) is in
determining the polarity of the check word As is the case
with the Ethernet polynomial the check word can be invert-
ed when it is appended to the data stream or as is the case
with the other polynomials the residue is appended with no
inversion Thirdly the ROM contains a bit (C1) which is used
to select the RFB input instead of the SEI input to be fed
into the LSB This is used when the polynomial selected is
actually a residue (least significant) stored in the ROM
which indicates whether the selected location is a polynomi-
al or a residue If the latter then it inhibits the RFB input
As mentioned previously upon a successful data transmis-
sion the CRC register has a zero residue There is an ex-
ception to this however with respect to the Ethernet poly-
nomial This polynomial upon a successful data transmis-
sion has a non-zero residue in the CRC register (C7 04 DD
7B)16 In order to provide a no-error indication two ROM
locations have been preloaded with the residue so that by
selecting these locations and clocking the device one addi-
tional time after the last check bit has been entered will
result in zeroing the CRC register In this manner a no-error
indication is achieved
With the present mix of polynomials the largest is 56th or-
der requiring four devices while the smallest is 16th order
requiring just one device In order to accommodate multi-
plexing between high order polynomials (X 16th order) and
lower order polynomials a location of all zeros is provided
This allows the user to choose a lower order polynomial
even if the system is configured for a higher order one
The ’F402 expandable CRC generator checker contains 6
popular CRC polynomials 2-16th Order 2-32nd Order 1-
48th Order and 1-56th Order The application diagram
shows the ’F402 connected for a 56th Order polynomial
Also shown are the input patterns for other polynomials
When the ’F402 is used with a gated clock disabling the
clock in a HIGH state will ensure no erroneous clocking
occurs when the clock is re-enabled Preset and Master Re-
set are asynchronous inputs presetting the register to S or
clearing to 1s respectively (note Ethernet residue and 56th
Order select code 8 LSB are exceptions to this)
To generate a CRC the pattern for the selected polynomial
is applied to the S inputs the register is preset or cleared as
required clock is enabled CWG is set HIGH data is applied
to D input output data is on D CW When the last data bit
has been entered CWG is set LOW and the register is
clocked for n bits (where n is the order of the polynomial)
The clock may now be stopped if desired (holding CWG
LOW and clocking the register will output zeros from D CW
after the residue has been shifted out)
To check a CRC the pattern for the selected polynomial is
applied to the S inputs the register is preset or cleared as
required clock is enabled CWG is set HIGH the data
stream including the CRC is applied to D input When the
last bit of the CRC has been entered the ER output is
checked HIGHeerror free data LOWecorrupt data The
clock may now be stopped if desired
To implement polynomials of lower order than 56th select
the number of packages required for the order of polynomial
and apply the pattern for the selected polynomial to the S
inputs (0000 on S inputs disables the package from the
feedback chain)
4

4페이지










74F402 전자부품, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
tPLH
tPHL
tPHL
tPLH
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay
CP to D CW
Propagation Delay
CP to RO
Propagation Delay
CP to ER
Propagation Delay
P to D CW
Propagation Delay
P to RO
Propagation Delay
P to ER
Propagation Delay
MR to D CW
Propagation Delay
MR to RO
Propagation Delay
MR to ER
Propagation Delay
D to D CW
Propagation Delay
CWG to D CW
Propagation Delay
Sn to D CW
74F
TA e a25 C
VCC e a5 0V
CL e 50 pF
Min Typ Max
30 45
8 5 15 0 19 0
10 5 18 0 23 0
8 0 13 5 17 0
8 0 14 0 18 0
15 5 26 0 33 0
8 5 14 5 18 5
11 0 18 5 23 5
11 5 19 5 24 5
9 5 16 0 20 5
10 0
10 5
11 0
90
17 0
18 0
19 0
15 5
21 5
23 0
24 0
19 5
16 5
60
75
65
70
11 5
95
28 0
10 5
12 0
11 0
12 0
19 5
16 0
35 5
13 5
16 0
14 0
15 5
24 5
20 0
54F
TA VCC e Mil
CL e 50 pF
Min Max
30
7 5 26 5
9 5 26 5
7 0 26 0
7 0 22 5
14 0 38 5
7 5 23 5
10 0 31 0
10 5 32 0
8 5 31 5
9 0 26 0
9 5 29 0
10 0 28 5
8 0 23 5
14 5 39 0
5 0 19 5
6 5 20 0
5 5 21 5
6 0 21 5
9 0 29 0
8 5 25 0
74F
TA VCC e Com
CL e 50 pF
Min
30
75
95
70
70
14 0
75
10 0
10 5
Max
21 0
25 0
19 0
20 0
35 0
20 5
25 5
26 5
8 5 22 5
Units
MHz
ns
ns
ns
ns
ns
90
95
10 0
80
23 5
25 5
26 0
21 5
ns
ns
ns
14 5
50
65
55
60
10 5
85
37 5
15 0
18 0
15 5
17 5
26 5
22 0
ns
ns
ns
ns
7

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