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부품번호 74F433SPC 기능
기능 First-In First-Out (FIFO) Buffer Memory
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74F433SPC 데이터시트, 핀배열, 회로
www.DataSheet4U.com
April 1988
Revised August 1999
74F433
First-In First-Out (FIFO) Buffer Memory
General Description
The 74F433 is an expandable fall-through type high-speed
First-In First-Out (FIFO) Buffer Memory that is optimized for
high-speed disk or tape controller and communication
buffer applications. It is organized as 64-words by 4-bits
and may be expanded to any number of words or any num-
ber of bits in multiples of four. Data may be entered or
extracted asynchronously in serial or parallel, allowing eco-
nomical implementation of buffer memories.
The 74F433 has 3-STATE outputs that provide added ver-
satility, and is fully compatible with all TTL families.
Features
s Serial or parallel input
s Serial or parallel output
s Expandable without additional logic
s 3-STATE outputs
s Fully compatible with all TTL families
s Slim 24-pin package
s 9423 replacement
Ordering Code:
Order Number Package Number
Package Description
74F433SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009544
www.fairchildsemi.com




74F433SPC pdf, 반도체, 판매, 대치품
FIGURE 2. Final Positions in an 74F433
Resulting from a 256-Bit Serial Train
Fall-Through Stack—The outputs of flip-flops F0–F3 feed
the stack. A LOW level on the Transfer to Stack (TTS) input
initiates a fall-through action; if the top location of the stack
is empty, data is loaded into the stack and the input register
is re-initialized. (Note that this initialization is delayed until
PL is LOW). Thus, automatic FIFO action is achieved by
connecting the IRF output to the TTS input.
An RS-type flip-flop (the initialization flip-flop) in the control
section records the fact that data has been transferred to
the stack. This prevents multiple entry of the same word
into the stack even though IRF and TTS may still be LOW;
the initialization flip-flop is not cleared until PL goes LOW.
Once in the stack, data falls through automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F433, the master reset (MR) input only initializes
the stack control section and does not clear the data.
Output Register
The Output Register (see Figure 3) receives 4-bit data
words from the bottom stack location, stores them, and out-
puts data on a 3-STATE, 4-bit parallel data bus or on a 3-
STATE serial data bus. The output section generates and
receives the necessary status and control signals.
Parallel Extraction—When the FIFO is empty after a LOW
pulse is applied to the MR input, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the output register, if the Transfer Out
Parallel (TOP) input is HIGH. As a result of the data trans-
fer, ORE goes HIGH, indicating valid data on the data out-
puts (provided that the 3-STATE buffer is enabled). The
TOP input can then be used to clock out the next word.
When TOP goes LOW, ORE also goes LOW, indicating
that the output data has been extracted; however, the data
itself remains on the output bus until a HIGH level on TOP
permits the transfer of the next word (if available) into the
output register. During parallel data extraction, the serial
output clock (CPSO) line should be LOW. The Transfer Out
Serial (TOS) line should be grounded for single-slice oper-
ation or connected to the appropriate ORE line for
expanded operation (refer to the “Expansion” section).
The TOP signal is not edge-triggered. Therefore, if TOP
goes HIGH before data is available from the stack but data
becomes available before TOP again goes LOW, that data
is transferred into the output register. However, internal
control circuitry prevents the same data from being trans-
ferred twice. If TOP goes HIGH and returns to LOW before
data is available from the stack, ORE remains LOW, indi-
cating that there is no valid data at the outputs.
Serial Extraction—When the FIFO is empty after a LOW
is applied to the MR input, the ORE output is LOW. After
data has been entered into the FIFO and has fallen through
to the bottom stack location, it is transferred into the output
register, if the TOS input is LOW and TOP is HIGH. As a
result of the data transfer, ORE goes HIGH, indicating that
valid data is in the register.
The 3-STATE Serial Data Output (QS) is automatically
enabled and puts the first data bit on the output bus. Data
is serially shifted out on the HIGH-to-LOW transition of
CPSO. To prevent false shifting, CPSO should be LOW
when the new word is being loaded into the output register.
The fourth transition empties the shift register, forces ORE
LOW, and disables the serial output, QS. For serial opera-
tion, the ORE output may be tied to the TOS input, request-
ing a new word from the stack as soon as the previous one
has been shifted out.
Expansion
Vertical Expansion—The 74F433 may be vertically
expanded, without external components, to store more
words. The interconnections necessary to form a 190-word
by 4-bit FIFO are shown in Figure 4. Using the same tech-
nique, any FIFO of (63n+1)-words by 4-bits can be config-
ured, where n is the number of devices. Note that
expansion does not sacrifice any of the 74F433 flexibility
for serial/parallel input and output.
www.fairchildsemi.com
4

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74F433SPC 전자부품, 판매, 대치품
positions of bits in an expanded 74F433 FIFO resulting
from a 2032-bit serial bit train.
Interlocking Circuitry—Most conventional FIFO designs
provide status signal analogous to IRF and ORE. However,
when these devices are operated in arrays, variations in
unit-to-unit operating speed require external gating to
ensure that all devices have completed an operation. The
74F433 incorporates simple but effective 'master/slave'
interlocking circuitry to eliminate the need for external gat-
ing.
In the 74F433 array of Figure 6, devices 1 and 5 are the
row masters; the other devices are slaves to the master in
their rows. No slave in a given row initializes its input regis-
ter until it has received a LOW on its IES input from a row
master or a slave of higher priority.
Similarly, the ORE outputs of slaves do not go HIGH until
their inputs have gone HIGH. This interlocking scheme
ensures that new input data may be accepted by the array
when the IRF output of the final slave in that row goes
HIGH and that output data for the array may be extracted
when the ORE output of the final slave in the output row
goes HIGH.
The row master is established by connecting its IES input
to ground, while a slave receives its IES input from the IRF
output of the next-higher priority device. When an array of
74F433 FIFOs is initialized with a HIGH on the MR inputs
of all devices, the IRF outputs of all devices are HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization.
Figure 10 is a conceptual logic diagram of the internal cir-
cuitry that determines master/slave operation. When MR
and IES are LOW, the master latch is set. When TTS goes
LOW, the initialization flip-flop is set. If the master latch is
HIGH, the input register is immediately initialized and the
initialization flip-flop reset. If the master latch is reset, the
input register is not initialized until IES goes LOW. In array
operation, activating TTS initiates a ripple input register ini-
tialization from the row master to the last slave.
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack oper-
ation and sets the ORE request flip-flop. If the master latch
is set, the last output register flip-flop is set and the ORE
line goes HIGH. If the master latch is reset, the ORE output
is LOW until a Serial Output Enable (OES) input is
received.
FIGURE 5. A Horizontal Expansion Scheme
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74F433SPC

First-In First-Out (FIFO) Buffer Memory

Fairchild
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