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74FR16245QC 데이터시트 PDF




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부품번호 74FR16245QC 기능
기능 16-Bit Transceiver with 3-STATE Outputs
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74FR16245QC 데이터시트, 핀배열, 회로
October 1989
Revised August 1999
74FR16245
16-Bit Transceiver with 3-STATE Outputs
General Description
The 74FR16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus-
oriented applications. Current sinking capability is 64 mA
on both the A and B Ports. The device is byte controlled.
Each byte has separate control inputs which can be
shorted together for full 16-bit operation. The transmit/
receive (T/Rn) inputs determine the direction of data flow
through the transceiver. The output enable (OEn) inputs
disable both A and B Ports by placing them in an high
impedance state.
Features
s Non-inverting buffers
s Bidirectional data paths
s A and B output sink capability of 64 mA, source
capability of 15 mA
s Separate control pins for each byte
s Guaranteed pin-to-pin skew
s Low 3-STATE IIL
s 16-Bit version of the 74F245 or 74F645
Ordering Code:
Order Number Package Number
Package Description
74FR16245QC
V44A
44-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.650 Square
74FR16245SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for SSOP
Pin Assignment for PLCC
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS010614
www.fairchildsemi.com




74FR16245QC pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
An to Bn or Bn to An
Output Enable Time
Output Disable Time
Extended AC Characteristics
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
1.3 2.7 4.3
1.3 2.2 4.3
3.9 6.9 13.9
3.9 9.7 13.9
1.8 3.9 6.3
1.8 4.4 6.3
TA = 0°C to +70°C
VCC = +5.0V
CL = 50 pF
Min Max
1.3 4.3
1.3 4.3
3.9 13.9
3.9 13.9
1.8 6.3
1.8 6.3
Unit
ns
ns
ns
TA = 0°C to +70°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
Symbol
Parameter
CL = 50 pF
16 Outputs Switching
CL = 250 pF
Unit
(Note 4)
(Note 5)
Min Max Min Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 3)
Propagation Delay
An to Bn or Bn to An
Output Enable Time
Output Disable Time
Pin-to-Pin Skew
for HL Transitions
1.3 5.8 3.2
1.3 5.8 3.2
3.9 14.6
3.9 14.6
1.8 6.3
1.8 6.3
1.2
8.2
8.2
ns
ns
ns
ns
tOSLH
(Note 3)
Pin-to-Pin Skew
for LH Transitions
2.2 ns
tOST
(Note 3)
Pin-to-Pin Skew
for HL/LH Transitions
2.5 ns
Note 3: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW (tOSHL) LOW-to-HIGH (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH (tOST). Specifications guaran-
teed with all outputs switching in phase.
Note 4: This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 5: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
www.fairchildsemi.com
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