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74FR16540QC 데이터시트 PDF




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부품번호 74FR16540QC 기능
기능 16-Bit Buffer/Line Driver with 3-STATE Outputs
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74FR16540QC 데이터시트, 핀배열, 회로
October 1989
Revised August 1999
74FR16540
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR16540 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is byte controlled. Each byte has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
Features
s Inverting buffers
s 3-STATE outputs drive bus lines
s Output sink capability of 64 mA, source capability of
15 mA
s Separate 3-STATE control pins for each byte
s Guaranteed 4000V minimum ESD protection
s Guaranteed multiple output switching, 250 pF delays
and pin-to-pin skew
s 16-bit version of the 74F540, 74F240, or 74FR240
Ordering Code:
Order Number Package Number
Package Description
74FR16540QC
V44A
44-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.650 Square
74FR16540SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for SSOP
Pin Assignment for PLCC
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS010615
www.fairchildsemi.com




74FR16540QC pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
In to On
Output Enable Time
Output Disable Time
Extended AC Characteristics
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
1.0 2.8 4.3
1.0 2.0 4.3
3.4 5.6 11.6
3.4 7.8 11.6
1.8 4.0 6.6
1.8 4.4 6.6
TA = 0°C to +70°C
VCC = +5.0V
CL = 50 pF
Min Max
1.0 4.3
1.0 4.3
3.4 11.6
3.4 11.6
1.8 6.6
1.8 6.6
Units
ns
ns
ns
TA = 0°C to +70°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
Symbol
Parameter
CL = 50 pF
16 Outputs Switching
CL = 250 pF
Units
(Note 4)
(Note 5)
Min Max Min Max
tPLH Propagation Delay
tPHL In to On
1.0 6.0 3.2 8.2
1.0 6.0 3.2 8.2
ns
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 3)
Output Enable Time
Output Disable Time
Pin-to-Pin Skew
for HL Transitions
3.4 14.5
3.4 14.5
1.8 6.6
1.8 6.6
1.4
ns
ns
ns
tOSLH
(Note 3)
Pin-to-Pin Skew
for LH Transitions
1.6
ns
tOST
(Note 3)
Pin-to-Pin Skew
for HL/LH Transitions
3.0 ns
Note 3: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH, (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH, (tOST). Specifications guaran-
teed with all outputs switching in phase. This specification is guaranteed but not tested.
Note 4: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 5: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
www.fairchildsemi.com
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부품번호상세설명 및 기능제조사
74FR16540QC

16-Bit Buffer/Line Driver with 3-STATE Outputs

Fairchild
Fairchild

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