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PDF 74FST3257 Data sheet ( Hoja de datos )
| Número de pieza | 74FST3257 | |
| Descripción | Quad 2:1 Multiplexer/ Demultiplexer Bus Switch | |
| Fabricantes | ON | |
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74FST3257
Quad 2:1 Multiplexer/
Demultiplexer Bus Switch
The ON Semiconductor 74FST3257 is a quad 2:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low RON and adds nearly zero propagation delay.
The device adds no noise or ground bounce to the system.
Features
• RON t 4 W Typical
• Less Than 0.25 ns−Max Delay Through Switch
• Nearly Zero Standby Current
• No Circuit Bounce
• Control Inputs are TTL/CMOS Compatible
• Pin−For−Pin Compatible With QS3257, FST3257, CBT3257
• All Popular Packages: SOIC−16, TSSOP−16, QFN16
• These Devices are Pb−Free and are RoHS Compliant
S
1B1
1B2
1A
2B1
2B2
2A
GND
1
2
3
4
5
6
7
8
16 VCC
15 OE
14 4B1
13 4B2
12 4A
11 3B1
10 3B2
9 3A
1B1 2
S VCC
1 16
1B2 3
1A 4
GND
2B1 5
2B2 6
2A 7
89
GND 3A
15 OE
14 4B1
13 4B2
12 4A
11 3B1
10 3B2
Figure 1. 16−Lead Pinout Diagrams
S OE Function
X H Disconnect
LL
HL
A = B1
A = B2
Figure 2. Truth Table
http://onsemi.com
16
1
SOIC−16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
16
FST3257G
AWLYWW
1
16
1
TSSOP−16
DT SUFFIX
CASE 948F
16
FST
3257
ALYW G
G
1
1
QFN16
MN SUFFIX
CASE 485AW
3257
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN NAMES
Pin
OE1, OE2
S0, S1
A
B1, B2, B3, B4
Description
Bus Switch Enables
Select Inputs
Bus A
Bus B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1
Publication Order Number:
74FST3257/D
1 page  
74FST3257
AC Loading and Waveforms
FROM
OUTPUT
UNDER
TEST
VI
500 W
CL* 500 W
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 4. AC Test Circuit
SWITCH
INPUT
10 %
tPLH
tf = 2.5 nS
90 %
1.5 V
90 %
1.5 V
OUTPUT
1.5 V
tf = 2.5 nS
3.0 V
10 %
tPLH
GND
VOH
1.5 V
VOL
Figure 5. Propagation Delays
ENABLE
INPUT
tf = 2.5 nS
90 %
1.5 V
tPZL
OUTPUT
tPZH
OUTPUT
10 % 10 %
1.5 V
1.5 V
tf = 2.5 nS
90 % 3.0 V
1.5 V
GND
tPLZ
VOL + 0.3 V
VOL
tPHZ
VOH
VOH − 0.3 V
Figure 6. Enable/Disable Delays
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74FST3257.PDF ] | |
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