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PDF MN89303A Data sheet ( Hoja de datos )
| Número de pieza | MN89303A | |
| Descripción | SVGA Display Controller | |
| Fabricantes | Panasonic | |
| Logotipo |  |
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For Information Equipment
MN89303A
SVGA Display Controller
Overview
The MN89303A is an LCD/CRT display controller with
IBM™ VGA-compatible registers. It features all the neces-
sary interfaces for a compact display system: ISA bus inter-
face, local bus interface, DRAM interface, and LCD panel
interface. The built-in graphics acceleration functions include
support for hardware cursor.
Note: IBM™ and VGA are registered trademarks of International
Business Machines Corporation.
Features
Monochrome STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
16-monochrome gradation
Color STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
16-gradation for each color (RGB)
Color TFT LCD panel support
Maximum display size: 800 × 600
4-bit output for each color (RGB)
Maximum number of colors in concurrent display
640 × 480: 256/4096 palette (TFT, STN)
800 × 600: 256/4096 palette (TFT, STN)
Built-in graphics acceleration functions
• Hardware cursor (16 × 16 or 32 × 32)
Built-in automatic display centering
Built-in gradation control table (rewritable) for
optimizing gradation to match panel
DRAM interface with 16-bit bus
• Choice of DRAM access timing to match
system performance (EDO/normal)
• Support for 2CAS/2WE mode
• Refresh control
Host interfaces
• ISA bus (16-bit)
• i386/i486 local bus (16-bit)
Note: i386 and i486 are trademarks of Intel Corporation.
Applications
Point-of-sale terminals, Factory automation terminals,
word processors, and other terminals
325
1 page  
For Information Equipment
MN89303A
Pin Descriptions (continued)
Pin No. Symbol I/O Level
Function Description
102 LCAS
O CMOS Lower Column Address Strobe (LCAS)
This output is the strobe signal for the lower column address latch.
In the 2WE mode, however, it functions as the LWE signal.
103 WE
O CMOS Write Enable
This output is the data write signal. In the 2WE mode, however, it
functions as the UWE signal.
104 to 121 MD[15:0] I/O TTL Memory Data
These pins represent the data bus to the DRAM.
31 BIOSEN O CMOS BIOS Enable
This output enables ROM BIOS output.
83 BACKON O CMOS Backlight ON
This output requests backlighting.
"L" level: OFF; "H" level: ON
84 LCDON O CMOS LCD Drive ON
This output requests power-ON for the LCD panel.
"L" level: OFF; "H" level: ON
85 LOGICON O CMOS LCD Logic ON
This output requests power-ON for LCD panel logic circuits.
"L" level: OFF; "H" level: ON
63 LP
O CMOS Line Pulse
This output provides pulses indicating the end of a line of the
LCD panel.
64 FP
O CMOS Frame Pulse
This output provides pulses indicating the start of a frame of the
LCD panel.
62 DISP
O CMOS Display Enable
This output enables the LCD display. An external RAMDAC uses
this signal as a blanking signal. A TFT LCD uses it as an enable
signal.
61 DCLK
O CMOS Data Shift Clock
This pin provides a data shift clock signal for an STN LCD panel.
It also outputs a dot clock signal on a TFT LCD panel or external
RAMDAC display mode.
65 to 72 UD[7:0]
O CMOS Upper Data[7:0]
75 to 82 LD[7:0]
O CMOS Lower Data[7:0]
This pins provide display data.
Usage varies with the LCD panel type.
5 Page 
For Information Equipment
Package Dimensions (Unit: mm)
QFH128-P-1818
96
20.0±0.2
18.0±0.2
97
65
64
MN89303A
128
1
(1.25)
33
32
0.5 0.2±0.1
1.0±0.2
0.1 SEATING PLANE
0.5±0.2
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MN89303A.PDF ] | |
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