PDF ST6387 Data sheet ( Hoja de datos )

Número de pieza	ST6387
Descripción	8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
Fabricantes	ST Microelectronics
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ST6365,ST6375,ST6385 R ST6367,ST6377,ST6387 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING s 4.5 to 6V supply operating range s 8MHz Maximum Clock Frequency s User Program ROM: up to 20140 bytes s Reserved Test ROM: up to 340 bytes s Data ROM: user selectable size s Data RAM: 256 bytes s Data EEPROM: 384 bytes s 42-Pin Shrink Dual in Line Plastic Package s Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs s Two Timers each including an 8-bit counter with a 7-bit programmable prescaler s Digital Watchdog Function s Serial Peripheral Interface (SPI) supporting S- BUS/ I 2 C BUS and standard serial protocols s SPI for external frequency synthesis tuning s 14 bit counter for voltage synthesis tuning s Up to Six 6-Bit PWM D/A Converters s AFC A/D converter with 0.5V resolution s Five interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR INT.) s On-chip clock oscillator s 5 Lines by 15 Characters On-Screen Display Generator with 128 Characters s All ROM types are supported by pin-to-pin EPROM and OTP versions. s The development tool of the ST6365, ST6375, ST6385, ST6367, ST6377, ST6387 microcon- trollers consists of the ST638X-EMU2 emula- tion and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer. PSDIP42 (Refer to end of Document for Ordering Information) DEVICE SUMMARY DEVICE ST6365 ST6367 ST6375 ST6377 ST6385 ST6387 ROM (Bytes) 8K 8K 14K 14K 20K 20K D/A Converter 4 6 4 6 4 6 Rev. 2.2 December 1997 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/84 1 1 page ST6365, ST6375, ST6385 ST6367, ST6377, ST6387 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6365,67,75,77,85,87 microcontrollers are members of the 8-bit HCMOS ST638x family, a series of devices specially oriented to TV applica- tions. Different ROM size and peripheral configu- rations are available to give the maximum applica- tion and cost flexibility. All ST638x members are based on a building block approach: a common core is surrounded by a combination of on-chip pe- ripherals (macrocells) available from a standard li- brary. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to TV applications. The macrocells of the ST638x family are: two Timer peripherals each including an 8-bit counter with a 7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DH- WD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), up to six 6-bit PWM D/A converters, an AFC A/D converter with 0.5V resolution, an on-screen display (OSD) with 15 characters per line and 128 characters (in two banks each of 64 characters). In addition the fol- lowing memory resources are available: program ROM (up to 20K), data RAM (256 bytes), EEP- ROM (384 bytes). Refer to pin configurations fig- ures and to ST638x device summary (Table 1) for the definition of ST638x family members and a summary of differences among the different types. Table 1. Device Summary Device ST6365 ST6367 ST6375 ST6377 ST6385 ST6387 ROM (Bytes) 8K 8K 14K 14K 20K 20K RAM (Bytes) 256 256 256 256 256 256 EEPROM (Bytes) 384 384 384 384 384 384 AFC Yes Yes Yes Yes Yes Yes VS D/A Colour Pins Yes 4 3 Yes 6 3 Yes 4 3 Yes 6 3 Yes 4 3 Yes 6 3 EPROM Devices ST63E85 ST63E87 ST63E85 ST63E87 ST63E85 ST63E87 5/84 5 Page ST6365, ST6375, ST6385 ST6367, ST6377, ST6387 MEMORY SPACES (Cont’d) 1.3.3 Data Space The ST6 Core instruction set operates on a specif- ic space, referred to as the Data Space, which contains all the data necessary for the program. The Data Space allows the addressing of RAM (256 bytes), EEPROM (384 bytes), ST6 Core and peripheral registers, as well as read-only data such as constants and look-up tables. Figure 6. Data Space DATA RAM/EEPROM/OSD BANK AREA DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER PROGRAM ROM PAGE REGISTER RESERVED SPI DATA REGISTER RESERVED TIMER 1 PRESCALER REGISTER TIMER 1 COUNTER REGISTER TIMER 1 STATUS/CONTROL REGISTER RESERVED WATCHDOG REGISTER 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0D1h 0D2h 0D3h 0D4h 0D5h 0D7h 0D8h RESERVED TIMER 2 PRESCALER REGISTER TIMER 2 COUNTER REGISTER TIMER 2 STATUS/CONTROL REGISTER RESERVED DA 0 DATA/CONTROL REGISTER DA 1 DATA/CONTROL REGISTER DA 2 DATA/CONTROL REGISTER DA 3 DATA/CONTROL REGISTER AFC, IR & OSD RESULT REGISTER OUTPUT CONTROL REGISTER 1 DA 4 DATA/CONTROL REGISTER DA 5 DATA/CONTROL REGISTER DEDICATED LATCHES CONTROL REGISTER EEPROM CONTROL REGISTER SPI CONTROL REGISTER 1 SPI CONTROL REGISTER 2 OSD CHARACTER BANK SELECT REGISTER VS DATA REGISTER 1 VS DATA REGISTER 2 RESERVED ACCUMULATOR OSD CONTROL REGISTERS LOCATED IN PAGE 6 OF BANKED DATA RAM VERTICAL START ADDRESS REGISTER HORIZONTAL START ADDRESS REGISTER VERTICAL SPACE REGISTER HORIZONTAL SPACE REGISTER BACKGROUND COLOUR REGISTER GLOBAL ENABLE REGISTER 0D9h 0DAh 0DBh 0DCh 0DDh 0DFh 0E0h 0E1h 0E2h 0E3h 0E5h 0E6h 0E7h 0E8h 0E9h 0EAh 0EBh 0ECh 0EDh 0EEh 0EFh 0F0h 0F5h 0FEh 0FFh 010h 011h 012h 013h 014h 017h 11/84 11 Page

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