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DG308ACY 데이터시트 PDF




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부품번호 DG308ACY 기능
기능 Quad Monolithic SPST / CMOS Analog Switch
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DG308ACY 데이터시트, 핀배열, 회로
Data Sheet
Quad Monolithic SPST, CMOS Analog
Switch
The DG308A quad monolithic SPST, CMOS switch is latch
proof and is designed to block signals up to 30VP-P when
OFF. Featuring low ON resistance, low power consumption,
and rail-to-rail analog signal range, this switch is ideally
suited for high speed switching applications in
communications, instrumentation and process control. The
DG308A has single and dual supply capability. The input
thresholds are CMOS compatible.
Ordering Information
PART NUMBER
DG308ACJ
DG308ACY
TEMP.
RANGE (oC)
PACKAGE
0 to 70 16 Ld PDIP
0 to 70 16 Ld SOIC
Pinout
DG308A
(PDIP, SOIC)
TOP VIEW
PKG.
NO.
E16.3
M16.15
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
-
16 IN2
15 D2
14 S2
13 V+ (SUB-
STRATE)
12 NC
11 S3
10 D3
9 IN3
DG308A
November 1999 File Number 3120.3
Features
• Low Power Consumption
• CMOS Compatible
±15V Analog Signal Range
• Single or Dual Supply Capability
• Alternate Source
Functional Diagram
DG308A
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
SWITCHES SHOWN FOR LOGIC “1” INPUT
TRUTH TABLE
LOGIC
DG308A
0 OFF
1 ON
Logic “0” 3.5V, Logic “1” 11V at V+ = 15V.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999




DG308ACY pdf, 반도체, 판매, 대치품
DG308A
Electrical Specifications
PARAMETER
V+ = 15V, V- = -15V, GND = 0V, TA = 25oC (Continued)
TEST CONDITIONS
(NOTE 4)
MIN
(NOTE 3)
TYP
(NOTE 4)
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, I-
All Channels ON or OFF
VIN = 0V or 15V
-
-100
0.001
-0.001
100
-
µA
µA
NOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
5. OFF isolation = 20 Log VD/VS, where VS = input to OFF switch, and VD = output.
Test Circuit and Waveforms
S
VS = 3V
IN
15V
V+
RL
VO = VS RL + rDS(ON)
D
VO
RL CL
1k35pF
GND
V-
-15V
LOGIC
INPUT
tr < 20ns
tf < 20ns 0V
LOGIC “1” = SWITCH ON
15V
50%
50%
SWITCH
INPUT
SWITCH
OUTPUT 0V
tON
90%
90%
tOFF
FIGURE 1. tON AND tOFF TEST CIRCUIT AND MEASUREMENT POINTS
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DG308ACY 전자부품, 판매, 대치품
DG308A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.0040 0.0098 0.10
0.25
-
B 0.013 0.020 0.33 0.51 9
C
0.0075 0.0098 0.19
0.25
-
D 0.3859 0.3937 9.80 10.00 3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC
1.27 BSC
-
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L 0.016 0.050 0.40 1.27 6
N 16
16 7
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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