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PDF DG536 Data sheet ( Hoja de datos )
| Número de pieza | DG536 | |
| Descripción | 16-Channel Wideband Video Multiplexers | |
| Fabricantes | Vishay Siliconix | |
| Logotipo |  |
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DG535/536
Vishay Siliconix
16-Channel Wideband Video Multiplexers
FEATURES
D Crosstalk: –100 dB @ 5 MHz
D 300 MHz Bandwidth
D Low Input and Output Capacitance
D Low Power: 75 mW
D Low rDS(on): 50 W
D On-Board Address Latches
D Disable Output
BENEFITS
D High Video Quality
D Reduced Insertion Loss
D Reduced Input Buffer
Requirements
D Minimizes Power Consumption
D Simplifies Bus Interface
APPLICATIONS
D Video Switching/Routing
D High Speed Data Routing
D RF Signal Multiplexing
D Precision Data Acquisition
D Crosspoint Arrays
D FLIR Systems
DESCRIPTION
The DG535/536 are 16-channel multiplexers designed for
routing one of 16 wideband analog or digital input signals to a
single output. They feature low input and output capacitance, low
on-resistance, and n-channel DMOS “T” switches, resulting in
wide bandwidth, low crosstalk and high “off” isolation. In the on
state, the switches pass signals in either direction, allowing them
to be used as multiplexers or as demultiplexers.
and a low 75-mW power consumption vastly reduces power
supply requirements.
Theses devices are built on a proprietary D/CMOS process
which creates low-capacitance DMOS FETs and high-speed,
low-power CMOS logic on the same substrate.
On-chip address latches and decode logic simplify
microprocessor interface. Chip Select and Enable inputs
simplify addressing in large matrices. Single-supply operation
For more information please refer to Vishay Siliconix
Application Note AN501 (FaxBack document number 70608).
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
GND 1
S8 2
S7 3
S6 4
S5 5
S4 6
S3 7
S2 8
S1 9
DIS 10
CS 11
CS 12
EN 13
A0 14
DG535
Latches/Decoders/Drivers
Top View
Dual-In-Line
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
28 S9
27 S10
26 S11
25 S12
24 S13
23 S14
22 S15
21 S16
20 D
19 V+
18 ST
17 A3
16 A2
15 A1
DG536
PLCC/Cerquad
6 5 4 3 2 1 44 43 42 41 40
DIS 7
CS 8
CS 9
EN 10
A0 11
A1 12
A2 13
A3 14
ST 15
V+ 16
D 17
Latches/
Decoders/
Drivers
39 S6
38 GND
37 S7
36 GND
35 S8
34 GND
33 S9
32 GND
31 S10
30 GND
29 S11
18 19 20 21 22 23 24 25 26 27 28
Top View
www.vishay.com
5-1
1 page  
DG535/536
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Logic Input Switching Threshold
vs. Supply Voltage (V+)
10
9 GND = 0 V
8 TA = 25_C
7
6
5
4
3
2
1
0
8 10 12 14 16
V+ – Positive Supply (V)
1 mA
100 nA
ID(on) vs. Temperature
V+ = +15 V
GND = 0 V
VD = VS = 3 V
10 nA
18
1 nA
Supply Current vs.
Supply Voltage and Temperature
14
12 GND = 0 V
10
125_C
8
25_C
6
4
–55_C
2
0
10 11 12 13 14 15 16 17 18
V+ – Positive Supply (V)
1 mA
100 nA
Leakage Current vs. Temperature
V+ = +15 V
GND = 0 V
10 nA
1 nA
ID(off)
IS(off)
100 pA
100 pA
10 pA
10 pA
1 pA
–55 –35 –15
5 25 45 65 85 105 125
Temperature (_C)
–120
–100
Adjacent Input Crosstalk vs. Frequency
DG536
RIN = 10 W
–80 DG536
RIN = 75 W
–60
DG535
–40 RIN = 10 W
–20 Test Circuit
See Figure 10
0
0.1
1
10
f – Frequency (MHz)
100
1 pA
–55 –35 –15
5 25 45 65 85 105 125
Temperature (_C)
–3 dB Bandwidth Insertion Loss vs. Frequency
0
–4
DG536
–8
–3 dB Points
–12
Test Circuit
–16
See Figure 6
RL = 50 W
DG535
–20
1
10 100
f – Frequency (MHz)
1000
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
www.vishay.com
5-5
5 Page 
DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
Since no PN junctions exist between the signal path and V+,
positive overvoltages are not a problem, unless the
breakdown voltage of the DMOS drain terminal (see Figure
13) (+18 V) is exceeded. Positive overvoltage conditions must
not exceed +18 V with respect to the GND pin. If this condition
is possible (e.g. transients in the signal), then a diode or Zener
clamp may be used to prevent breakdown.
being coupled back to the analog signal source and C2 blocks
the dc bias from the output signal. Both C1 and C2 should be
tantalum or ceramic disc type capacitors in order to operate
efficiently at high frequencies. Active bias circuits are
recommended if rapid switching time between channels is
required.
The overvoltage conditions described may exist if the supplies
are collapsed while a signal is present on the inputs. If this
condition is unavoidable, then the necessary steps outlined
above should be taken to protect the device
DC Biasing
An alternative method is to offset the supply voltages (see
Figure 15).
Decoupling would have to be applied to the negative supply to
ensure that the substrate is well referenced to signal ground.
Again the capacitors should be of a type offering good high
frequency characteristics.
To avoid negative overvoltage conditions and subsequent
distortion of ac analog signals, dc biasing may be necessary.
Biasing is not required, however, in applications where signals
are always positive with respect to the GND or substrate
connection, or in applications involving multiplexing of low
level (up to "200 mV) signals, where forward biasing of the
PN substrate-source/drain terminals would not occur.
Biasing can be accomplished in a number of ways, the
simplest of which is a resistive potential divider and a few dc
blocking capacitors as shown in Figure 14.
+15 V
Level shifting of the logic signals may be necessary using this
offset supply arrangement.
Analog
Signal
IN
Decoupling
Capacitors
+
+12 V
V+
S
DG536 D
GND
Analog
Signal
OUT
–3 V
Analog
Signal
C1
+
IN
R2
100 mF/16 V
Tantalum
R1
S
V+
DG536
GND
C2
+
D
Analog
Signal
OUT
100 mF/16 V
Tantalum
FIGURE 15.
DG536 with
Offset Supply
TTL to CMOS level shifting is easily obtained by using a
MC14504B.
FIGURE 14.
Simp
le Bias Circuit
R1 and R2 are chosen to suit the appropriate biasing
requirements. For video applications, approximately 3 V of
bias is required for optimal differential gain and phase
performance. Capacitor C1 blocks the dc bias voltage from
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
Circuit Layout
Good circuit board layout and extensive shielding is essential
for optimizing the high frequency performance of the DG536.
Stray capacitances on the PC board and/or connecting leads
will considerably degrade the ac performance. Hence, signal
paths must be kept as short as practically possible, with
extensive ground planes separating signal tracks.
www.vishay.com
5-11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet DG536.PDF ] | |
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