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DG611DY 데이터시트 PDF




Vishay Siliconix에서 제조한 전자 부품 DG611DY은 전자 산업 및 응용 분야에서
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부품번호 DG611DY 기능
기능 High-Speed / Low-Glitch D/CMOS Analog Switches
제조업체 Vishay Siliconix
로고 Vishay Siliconix 로고


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DG611DY 데이터시트, 핀배열, 회로
DG611/612/613
Vishay Siliconix
High-Speed, Low-Glitch D/CMOS Analog Switches
FEATURES
D Fast Switching— tON: 12 ns
D Low Charge Injection: "2 pC
D Wide Bandwidth: 500 MHz
D 5-V CMOS Logic Compatible
D Low rDS(on): 18 W
D Low Quiescent Power : 1.2 nW
D Single Supply Operation
BENEFITS
D Improved Data Throughput
D Minimal Switching Transients
D Improved System Performance
D Easily Interfaced
D Low Insertion Loss
D Minimal Power Consumption
APPLICATIONS
D Fast Sample-and-Holds
D Synchronous Demodulators
D Pixel-Rate Video Switching
D Disk/Tape Drives
D DAC Deglitching
D Switched Capacitor Filters
D GaAs FET Drivers
D Satellite Receivers
DESCRIPTION
The DG611/612/613 feature high-speed low-capacitance
lateral DMOS switches. Charge injection has been minimized
to optimize performance in fast sample-and-hold applications.
Each switch conducts equally well in both directions when on
and blocks up to 16 Vp-p when off. Capacitances have been
minimized to ensure fast switching and low-glitch energy. To
achieve such fast and clean switching performance, the
DG611/612/613 are built on the Vishay Siliconix proprietary
D/CMOS process. This process combines n-channel DMOS
switching FETs with low-power CMOS control logic and
drivers. An epitaxial layer prevents latchup.
The DG611 and DG612 differ only in that they respond to
opposite logic levels. The versatile DG613 has two normally
open and two normally closed switches. It can be given various
configurations, including four SPST, two SPDT, one DPDT.
For additional information see Applications Note AN207
(FaxBack number 70605).
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG611
IN1 1
D1 2
S1 3
V– 4
GND 5
S4 6
D4 7
IN4 8
Dual-In-Line
and SOIC
Top View
16 IN2
15 D2
14 S2
13 V+
12 VL
11 S3
10 D3
9 IN3
DG611
D1 IN1 NC IN2 D2
Key
3 2 1 20 19
S1
V–
NC
GND
S4
4
5
6
7
8
LCC
Top View
18 S2
17 V+
16 NC
15 VL
14 S3
9 10 11 12 13
D4 IN4 NC IN3 D3
Four SPST Switches per Package
TRUTH TABLE
Logic DG611 DG612
0 ON OFF
1
OFF
ON
Logic “0” v 1 V
Logic “1” w 4 V
Document Number: 70057
S-00399—Rev. G, 13-Sep-99
www.vishay.com S FaxBack 408-970-5600
4-1




DG611DY pdf, 반도체, 판매, 대치품
DG611/612/613
Vishay Siliconix
SPECIFICATIONSa FOR UNIPOLAR SUPPLIES
Parameter
Symbol
Analog Switch
Analog Signal Rangee
Switch On-Resistance
VANALOG
rDS(on)
Dynamic Characteristics
Turn-On Timee
Turn-Off Timee
tON
tOFF
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V– = –3 V
VL = 5 V, VIN = 4 V, 1 Vf
IS = –1 mA, VD = 1 V
RL = 300 W, CL = 3 pF, VS = 2 V
See Test Circuit, Figure 2
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
Tempb Typc Mind Maxd Mind Maxd Unit
Full 0 7 0 7 V
Room
25
60
60 W
Room
15
30
30
ns
Room
10
25
25
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. DQ = bQ at VS = 3 V – Q at VS = –3 Vb.
www.vishay.com S FaxBack 408-970-5600
4-4
Document Number: 70057
S-00399—Rev. G, 13-Sep-99

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DG611DY 전자부품, 판매, 대치품
DG611/612/613
Vishay Siliconix
TEST CIRCUITS
+5 V
+15 V
"2 V
VL
S
IN
GND
V+
D
V–
V–
VO
RL
300 W
CL
5V
Logic Input
0V
VS= "2 V
Switch Output
0V
FIGURE 2. Switching Time
50%
tr < 10 ns
tf < 10 ns
90%
20%
tON
tOFF
CL (includes fixture and stray capacitance)
VO = VS
RL
RL + rDS(on)
Rg
Vg
5V
+5 V
VL
S
IN
GND
+15 V
V+
D
V–
–3 V
VO
CL
1 nF
FIGURE 3. Charge Injection
+5 V
C
VS
Rg = 50 W
1 V, 4 V
NC
1 V, 4 V
XTALK Isolation = 20 log
C = RF bypass
VS
VO
VL
S1
IN1
S2
IN2
GND
+15 V
C
V+
D1
D2
V– C
–3 V
FIGURE 4. Crosstalk
50 W
VO
RL
APPLICATIONS
High-Speed Sample-and-Hold
In a fast sample-and-hold application, the analog switch
characteristics are critical. A fast switch reduces aperture
uncertainty. A low charge injection eliminates offset (step)
errors. A low leakage reduces droop errors. The CLC111, a fast
input buffer, helps to shorten acquisition and settling times. A
low leakage, low dielectric absorption hold capacitor must
be used. Polycarbonate, polystyrene and polypropylene
are good choices. The JFET output buffer reduces droop
due to its low input bias current. (See Figure 5.)
Pixel-Rate Switch
Windows, picture-in-picture, title overlays are economically
generated using a high-speed analog switch such as the
DG613. For this application the two video sources must be
sync locked. The glitch-less analog switch eliminates halos.
(See Figure 6.)
Document Number: 70057
S-00399—Rev. G, 13-Sep-99
GaAs FET Drivers
Figure 7 illustrates a high-speed GaAs FET driver. To turn the
GaAs FET on 0 V are applied to its gate via S1, whereas to turn
it off, –8 V are applied via S2. This high-speed, low-power
driver is especially suited for applications that require a large
number of RF switches, such as phased array radars.
www.vishay.com S FaxBack 408-970-5600
4-7

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