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PDF DG9421 Data sheet ( Hoja de datos )
| Número de pieza | DG9421 | |
| Descripción | Precision Low-Voltage / Low-Glitch CMOS Analog Switches | |
| Fabricantes | Vishay Siliconix | |
| Logotipo |  |
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DG9421, DG9422
Vishay Siliconix
Precision Low-Voltage, Low-Glitch CMOS Analog Switches
DESCRIPTION
Using BiCMOS wafer fabrication technology allows the
DG9421, DG9422 to operate on single and dual supplies.
Designed for optimal performance at single 5 V and
dual ± 5 V, the DG9421, DG9422 combine low and flat
on-resistance (3 Ω), fast speed (tON = 38 ns) and is well
suited for applications where signal switching accuracy, low
noise and low distortion is critical.
The DG9421 and DG9422 respond to opposite control logic
as shown in the Truth Table.
FEATURES
• 2.7 V thru 12 V single supply or ± 2.7 V
thru ± 6 V dual supply
• Low on-resistance - RDS(on): 2 Ω at 12 V
• Fast switching - tON: 22 ns
- tOFF: 28 ns
• TTL and low voltage logic
Available
Available
• Low leakage: 10 pA (typ.)
• > 2000 V ESD protection
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
BENEFITS
• High accuracy
• High speed, low glitch
• Single and dual supply capability
• Low RON in small TSOP package
• Low leakage
• Low power consumption
APPLICATIONS
• Automatic test equipment
• Data acquisition
• XDSL and DSLAM
• PBX systems
• Reed relay replacement
• Audio and video signal routing
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
V+
COM
V-
1
2
3
TSOP-6
6 IN
5 NC
4 GND
Top View
Device Marking:
DG9421DV = 4Exxx
V+
COM
V-
1
2
3
TSOP-6
6 IN
5 NO
4 GND
Top View
Device Marking:
DG9422DV = 4Fxxx
TRUTH TABLE
LOGIC
0
1
DG9421
ON
OFF
Notes
• Logic “0” ≤ 0.8 V
• Logic “1” ≥ 2.4 V
• Switches shown for logic “0” input
ORDERING INFORMATION
TEMP. RANGE
PACKAGE
-40 °C to +85 °C
6 / Pin TSOP
DG9422
OFF
ON
PART NUMBER
DG9421DV-T1
DG9421DV-T1-E3
DG9422DV-T1
DG9422DV-T1-E3
S14-2339-Rev. H, 08-Dec-14
1
Document Number: 70679
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
www.vishay.com
DG9421, DG9422
Vishay Siliconix
SPECIFICATIONS a (Single Supply 3 V)
PARAMETER
Analog Switch
Analog Signal Range e
Drain-Source
On-Resistance
Switch Off
Leakage Current g
Channel-On
Leakage Current g
Digital Control
Input Current, VIN Low e
Input Current, VIN High e
Dynamic Characteristics
Turn-On Time
Turn-Off Time
Charge Injection e
Off-Isolation e
Source Off Capacitance e
Drain Off Capacitance e
Channel On Capacitance e
SYMBOL
VANALOG
RDS(on)
IS(off)
ID(off)
ID(on)
IIL
IIH
tON
tOFF
Q
OIRR
CS(off)
CD(off)
CD(on)
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
V+ = 3 V, V- = 0 V, VIN = 0.4 V f
V+ = 2.7 V, V- = 0 V
IS = 5 mA, VD = 0.5 V, 2.2 V
V+ = 3.3 V, V- = 0 V
VS = 1, 2 V, VD = 2 V, 1 V
V+ = 3.3 V, V- = 0 V
VD = VS = 1 V, 2 V
VIN under test = 0.4 V
VIN under test = 2.4 V
RL = 300 Ω, CL = 35 pF, VS = 1.5 V
see figure 2
Vg = 0 V, Rg = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
f = 1 MHz
TEMP. b
LIMITS
-40 °C to +85 °C
MIN. d TYP. c MAX. d
UNIT
Full 0 - 3 V
Room
Full
-
-
7.3 8.8
Ω
- 10.1
Room
-1
-
1
Full -10
-
10
Room
Full
-1
-10
-
-
1
nA
10
Room
-1
-
1
Full -10
-
10
Full -1 0.02 1
μA
Full -1 0.02 1
Room
Full
Room
Full
Room
Room
Room
Room
Room
90 110
125
ns
32 84
99
31 pC
-60 dB
35
34 pF
77
Notes
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. Leakage parameters are guaranteed by worst case test conditions and not subject to test.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S14-2339-Rev. H, 08-Dec-14
5
Document Number: 70679
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
AN823
Vishay Siliconix
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
0.014
0.35
0.026
0.65
0.074
1.875
0.122
3.1
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 1. Recommended Copper Spreading Footprint
Document Number: 71743
27-Feb-04
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Ramp-Up Rate
Temperature @ 155 " 15_C
Temperature Above 180_C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
+6_C/Second Maximum
120 Seconds Maximum
70 − 180 Seconds
240 +5/−0_C
20 − 40 Seconds
+6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
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1
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DG9421.PDF ] | |
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