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PDF DIR1701 Data sheet ( Hoja de datos )
| Número de pieza | DIR1701 | |
| Descripción | DIGITAL AUDIO INTERFACE RECEIVER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DIR1701 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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DIR1701
SLAS331 – APRIL 2001
DIGITAL AUDIO INTERFACE RECEIVER
FEATURES
D Standard Digital Audio Interface Receiver
(EIAJ1201)
D Sampling Rate: 32/44.1/48/88.2/96 kHz
D Recover 128 / 256 / 384 / 512 fs System Clock
D Very Low Jitter System Clock Output (80ps
Typically)
D On-Chip Master Clock Oscillator, Only an
External 12.000 MHz or 16.000 MHz Crystal Is
Required
D Selectable Output PCM Audio Data Format
D Output User Bit Data, Flag Signals, and
Channel Status Data With Block Start Signal
D Single + 3.3-V Power Supply
D Package: 28 SSOP
APPLICATIONS
D AV Receiver
D MD Player
D DAC Unit
DESCRIPTION
The DIR1701 is a digital audio interface receiver
(DIR) which receives and decodes audio data up
to 96 kHz according to the AES/EBU, IEC958,
S/PDIF, and EIAJCP340/1201 consumer and
professional format interface standards. The
DIR1701 demultiplexes the channel status bit and
user bit directly to serial output pins, and has
dedicated output pins for the most important
channel status bits.
The significant advantages of the DIR1701 are
96 kHz sampling rate capability and Low-jitter
clock recovery by the Sampling Period Adaptive
Controlled Tracking (SpAct) system. Input signal
is reclocked with the patented Sampling period
Adaptive controlled tracking system for maximum
quality. These two features are required for recent
consumer and professional audio instruments, in
which the DIR has an interface to any kind of
delta-sigma type ADC/DAC with 96 kHz sampling
rate.
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct and Burr-Brown are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright 2001, Texas Instruments Incorporated
1
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DIR1701
SLAS331 – APRIL 2001
electrical characteristics, all specifications at TA = 25°C, VCC = VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
VIH (5)
VIL (5)
VIH2 (6)
VIL2 (6)
VIH3 (7)
VIL3 (7)
VOH (8)
VOL (8)
VOH (9)
VOL (9)
IIH(10)
IIL(10)
IIH(11)
IIL(11)
IIH(6)
IIL(6)
fs(12)
Input logic level
Output logic level
Input leakage current
Input sampling frequency
SCKO
System clock frequency
tj SCKO clock jitter
SCKO duty cycle
IO = 1 mA
IO = –2 mA
IO = 2 mA
IO = –4 mA
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
2
70%VDD
70%VDD
VDD–0.4
VDD–0.4
–10
–10
–100
–10
–10
32
4.096
65
–65
128/256/
384/512 fs
80
50%
5.5
0.8
30%VDD
5.5
30%VDD
0.5
0.5
100
10
10
10
10
96
49.152
VDC
VDC
µA
kHz
MHz
ps RMS
XTI clock accuracy
–500
See
Table 3
500 ppm
S/PDIF INPUT
Duty cycle
Jitter
POWER SUPPLY REQUIREMENTS
VIN = 1.5 V, fs = 96 kHz
VIN = 1.5 V
15%
85%
20 ns p-p
VDD, VCC Voltage range
ICC (VCC) Supply current (see Note 13)
IDD (VDD)
PD Power dissipation
POWER SUPPLY REQUIREMENTS
3 3.3 3.6 VDC
3.4 4.7
mA
26 36
100 mW
Operation temperature
–25 85 °C
θJA Thermal resistance
28-pin SSOP
100 °C/W
NOTES: 5. TTL compatible, except pins 8, 20: XTI, DIN.
6. Pin 8: XTI (CMOS logic level).
7. Pin 20: DIN (CMOS logic level).
8. Pins 1–3, 9, 17–18, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK.
9. Pins 4, 10–12, 15–16: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT.
10. Pins 13–14, 19–20, 25–26, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL.
11. Pin 21: RST
12. fs is defined as the incoming audio sampling frequency per channel.
13. No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock
frequency.
www.ti.com
5
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DIR1701
SLAS331 – APRIL 2001
unlock flag minimum pulse width time (continued)
CASE-B when parity error occurs
When a parity error occurs in one subframe interval, UNLOCK becomes HIGH during this sub-frame then
returns LOW at the next arriving subframe.
During this subframe with parity error, the data output will hold the previous data of each channel.
CASE-B When Parity Error Occurs
UNLOCK
H
L
LRCKO
BCKO
DOUT
24
1
24 1 2
Same as The Previous Data
Figure 6. UNLOCK Timing for Parity Error
PCM audio interface
The DIR1701 can produce 16-bit or 24-bit output data in standard format and 24-bit output data in IIS format.
The PCM audio interface format of the DIR1701 is selected using the format pins FMT1, FMT0. Table 6 shows
the FMT pin configuration.
Table 6. Audio Output Data Format Select
FMT1
LOW
LOW
HIGH
HIGH
FMT0
LOW
HIGH
LOW
HIGH
AUDIO DATA FORMAT
16 bit MSB first, Right justified
24 bit MSB first, Right justified
24 bit MSB first, Left justified
24 bit IIS
www.ti.com
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet DIR1701.PDF ] | |
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