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DIR1703 데이터시트 PDF




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부품번호 DIR1703 기능
기능 DIGITAL AUDIO INTERFACE RECEIVER
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DIR1703 데이터시트, 핀배열, 회로
DIR1703
SLES007– JULY 2001
DIGITAL AUDIO INTERFACE RECEIVER
FEATURES
D Standard Digital Audio Interface Receiver
(EIAJ1201)
D Sampling Rate: 32 / 44.1 / 48 / 88.2 / 96 kHz
D Recover 128 / 256 / 384 / 512 fs System Clock
D Very Low Jitter System Clock Output (75 ps
Typically)
D On-Chip Master Clock Oscillator, Only an
External Crystal Is Required:
24.576 / 22.5792 / 18.432 / 16.9344 / 16.384 /
12.288 / 11.2896 / 8.192 / 6.144 / 5.6448 /
4.096 MHz Crystals Are Available
D Selectable Output PCM Audio Data Format
D Selectable Crystal Clock and PPL Clock
Operation Mode
D Output User Bit Data, Flag Signals, and
Channel Status Data With Block Start Signal
D Single 3.3-V Power Supply
D Package: 28 SSOP
APPLICATIONS
D AV Receiver
D MD Player
D DAC Unit
DESCRIPTION
The DIR1703 is a digital audio interface receiver
(DIR) which receives and decodes audio data up
to 96 kHz according to the AES/EBU, IEC958,
S/PDIF, and EIAJCP340/1201 consumer and
professional format interface standards. The
DIR1703 demultiplexes the channel status bit and
user bit directly to serial output pins, and has
dedicated output pins for the most important
channel status bits. It also includes extensive
errors reporting.
The significant advantages of the DIR1703 are
96-kHz sampling rate capability and Low-jitter
clock recovery by the Sampling Period Adaptive
Controlled Tracking (SpAct) system. The input
signal is reclocked with the patented Sampling
period Adaptive controlled tracking system for
maximum quality. These features are required for
recent consumer and professional audio
instruments, in which the DIR has an interface to
any kind of delta-sigma type ADC/DAC with a
96-kHz sampling rate.
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct and Burr-Brown are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright 2001, Texas Instruments Incorporated
1




DIR1703 pdf, 반도체, 판매, 대치품
DIR1703
SLES007JULY 2001
absolute maximum ratings
Supply voltage, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Supply voltage differences, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage: Digital input pins except XTI . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to (6.5 V + 0.3 V)
XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to (VDD + 0.3 V)
Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4 www.ti.com

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DIR1703 전자부품, 판매, 대치품
DIR1703
SLES007JULY 2001
system clock output
The primary function of the DIR1703 is to recover audio data and a low jitter clock from a digital audio
transmission line. The system clock (SCKO) can be selected in two clocks that are generated by the crystal
oscillator clock (crystal mode) or the PLL clock (PLL mode) by the SpAct.
The two operation modes are selected by the CKSEL pin. In the PLL clock operation mode, the clock that can
be generated is SCKO (128 / 256 / 384 / 512 fS, shown in Table 1), BCKO (64 fS), and LRCKO (1 fS). SCKO
is the output of the voltage controlled oscillator (VCO) in an analog PLL. The PLL function consists of a VCO,
phase and frequency detector, and a external second-order loop filter. The closed-loop transfer function, which
specifies the PLL jitter attenuation characteristics, is shown in Figure 2. In the crystal clock operation mode,
SCKO can be generated from several crystal oscillators shown in Table 2.
The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins
BFRAME, EMFLG, URBIT, or CSBIT as shown in Table 3. A 12.288 MHz crystal resonator can be used for
96-kHz 128 fS (CSBIT), 48-kHz 256 fS (OPEN) and 32-kHz 384 fS (BFRAME). If BRSEL is not connected
to any pins, the 48-kHz sampling rate is selected. The system clock frequency of both modes can be selected
by control data at SCF0 and SCF1 pins shown in Table 4.
Table 5 shows the state of the system and the condition of audio clocks and flags in both the PLL and crystal
operation modes. In the crystal clock operation mode, SpAct also detects the bit rate of the incoming S/PDIF
signal and indicates the state at the UNLOCK pin. Therefore, by connecting CKSEL pin 28) to UNLOCK (pin
27), the system clock source can be selected automatically when the S/PDIF signal arrives and the bit rate is
detected. The required accuracy for clock frequency of the crystal resonator or external clock input is ±500 ppm.
Table 1. Generated System Clock (SCKO) PLL Clock Operation Mode
SAMPLING
RATE
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
128 fS
yes
yes
yes
yes
yes
256 fS
yes
yes
yes
yes
yes
384 fS
yes
yes
yes
yes
yes
512 fS
yes
yes
yes
yes
yes
0
20
40
60
80
100
100 1 k 10 k 100 k 1 M 10 M 100 M
f Frequency kHz
Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter
www.ti.com
7

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