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PDF MC33560 Data sheet ( Hoja de datos )
| Número de pieza | MC33560 | |
| Descripción | Power Management and Interface IC for Smartcard Readers and Couplers | |
| Fabricantes | ON Semiconductor | |
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MC33560
Power Management and
Interface IC for Smartcard
Readers and Couplers
The MC33560 is an interface IC for smartcard reader/writer
applications. It enables the management of any type of smart or memory
card through a simple and flexible microcontroller interface. Moreover,
several couplers can be coupled in parallel, thanks to the chip select input
pin (pin #5). The MC33560 is particularly suited to low power and
portable applications because of its power saving features and the
minimum of external parts required. Battery life is extended by the wide
operating range and the low quiescent current in stand by mode. A highly
sophisticated protection system guarantees timely and controlled
shutdown upon error conditions.
• 100% Compatible with ISO 7816–3 Standard
• Wide Battery Supply Voltage Range: 1.8V < VBAT < 6.6V
• Programmable VCC Supply for 3V or 5V Card Operation
• Power Management for Very Low Quiescent Current in Stand By
Mode (30µA max)
• Microprocessor Wake–up Signal Generated Upon Card Insertion
• Self Contained DC/DC Converter to Generate VCC using a Minimum
of Passive Components
• Controlled Power Up/Down Sequence for High Signal Integrity on
the Card I/O and Signal Lines
• Programmable Card Clock Generator
• Chip Select Capability for Parallel Coupler Operation
• High ESD Protection on Card Pins (4kV, Human Body Model)
• Fault Monitoring VBATlow, VCClow and ICClim
• All Card Outputs Current Limited and Short Circuit Protected
• Tested Operating Temperature Range: –25°C to +85°C
Figure 1. Simplified Functional Block Diagram
VBAT
L1
ILIM
PGND
PWRON
INT
RDYMOD
CS
DC/DC
CONVERTER
POWER
MANAGER
AND
PROGRAMMING
CARD
DETECTOR
DELAY
CRDDET
CRDCON
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24
1
SO–24L
DW SUFFIX
CASE 751E
TSSOP–24
DTB SUFFIX
CASE 948H
24
1
PIN CONNECTIONS
PGND 1
PWRON 2
INT 3
RDYMOD 4
CS 5
RESET 6
IO 7
INVOUT 8
ASYCLKIN 9
SYNCLK 10
CRDIO 11
CRDGND 12
24 ILIM
23 VBAT
22 L1
21 C4
20 C8
19 CRDC8
18 CRDCON
17 CRDDET
16 CRDC4
15 CRDCLK
14 CRDRST
13 CRDVCC
(Top View)
SYNCLK
ASYCLKIN
INVOUT
IO
RESET
C4
C8
CLOCK
GENERATOR
VBAT
LEVEL
TRANSLATOR
CRDVCC
CRDIO
CRDRST
CRDC4
CRDC8
CRDCLK
CRDGND
ORDERING INFORMATION
Device
Package
Shipping
MC33560DW
SO–24WB 30 Units/Rail
MC33560DWR2 SO–24WB 1000 Tape & Reel
MC33560DTB TSSOP–24 62 Units/Rail
MC33560DTBR2 TSSOP–24 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 1999
October, 1999 – Rev. 0
1
Publication Order Number:
MC33560/D
1 page  
MC33560
Figure 2. Maximum Battery and Card Supply
Current vs. VBAT (VCC=5V)
200
180 IBATop MAX
160
140
120 ICC MAX
100
80
60 Mode Sync
40
SYNCLK=4MHz
L1=47µH
20 Rlim=0
0
1.5 2.5 3.5 4.5 5.5 6.5 7.5
VBAT (V)
Figure 3. Maximum Battery and Card Supply
Current vs. VBAT (VCC=3V)
200
180 IBATop MAX
160
140
120 ICC MAX
100
80
60 Mode Sync
40
SYNCLK=4MHz
L1=47µH
20 Rlim=0
0
1.5 2.5 3.5 4.5 5.5 6.5 7.5
VBAT (V)
Figure 4. Battery Current vs. Input Clock Frequency
(ICC=0, VBAT=4V)
14
VBAT=4V
12 L1=47µH
Rlim=0
10 ICC=0
8
Async
Sync
6 Async/2
4
Async/4
2
0
0 2.0 4.0 6.0 8.0 10 12 14 16
Frequency (MHz)
Figure 5. Battery Current vs. Input Clock Frequency
(ICC =0, VBAT=2.5V)
14
VBAT=2.5V
12 L1=47µH
Rlim=0
10 ICC=0
8
Async
6
Sync
4
Async/2
2 Async/4
0
0 2.0 4.0 6.0 8.0 10 12 14 16
Frequency (MHz)
Figure 6. Maximum Battery Current vs. RLIM
(VCC=5V, VBAT=4V)
250
200 L1=100µH
Mode Sync
SYNCLK=4MHz
VBAT=4V
150
L1=47µH
100
50
L1=22µH
0
01 2345
Rlim (ohms)
Figure 7. Maximum Battery Current vs. RLIM
(VCC=3V, VBAT=2.5V)
250
200 L1=100µH
Mode Sync
SYNCLK=4MHz
VBAT=2.5V
150
L1=47µH
100
50
L1=22µH
0
01 2345
Rlim (ohms)
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5 Page 
MC33560
CARD VCC AND CARD CLOCK PROGRAMMING
The CRDVCC and ASYCLK programming options allow the system clock frequency to be matched to the card clock
frequency and to select 3V or 5V CRDVCC supply. Table 3 shows the values of PWRON, RESET and IO for the possible
options. The default power reset condition is state 4 (synchronous clock and CRDVCC =5V). All states are latched for each
output variable in programming mode at the positive transition of CS (see figure 20).
Table 3 : CARD VCC AND CARD CLOCK TRUTH TABLE
STATE#
PWRON
RESET
IO
CRDVCC
CRDCLK
0
L LL
3V SYNCLK
1
L LH
3V ASYCLKIN/4
2
L HH
3V ASYCLKIN/2
3
L HL
3V ASYCLKIN
4
H LL
5V SYNCLK
5
H LH
5V ASYCLKIN/4
6
H HH
5V ASYCLKIN/2
7
H HL
5V ASYCLKIN
Note : Card clock integrity is maintained during all frequency commutations (no spikes).
State 4 is the default state at power on.
DC/DC CONVERTER AND CARD DETECTOR STATUS
The MC33560 status can be polled when CS=L. Please consult table 2 for a description of input and output signals.The
significance of the status message is described in table 4.
Table 4 : RDYMOD STATUS MESSAGES
PWRON
(input)
RDYMOD
(output)
Message
LOW
LOW
No card
LOW
HIGH
Card present
HIGH
LOW
DC/DC converter overload
HIGH
HIGH
DC/DC converter OK
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MC33560.PDF ] | |
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