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Número de pieza | 2SJ680 | |
Descripción | Field Effect Transistor / Silicon P-Channel MOS Type | |
Fabricantes | Toshiba | |
Logotipo | ||
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2SJ680
TOSHIBA Field Effect Transistor Silicon P-Channel MOS Type (π-MOS V)
2SJ680
Switching Applications
Chopper Regulator, DC/DC Converter and
Motor Drive Applications
• Low drain-source ON-resistance: RDS (ON) = 1.6 Ω (typ.)
• High forward transfer admittance: |Yfs| = 2.0 S (typ.)
• Low leakage current: IDSS = −100 µA (max) (VDS = −200 V)
• Enhancement model: Vth = −1.5 ~ −3.5 V (VDS = −10 V, ID = −1 mA)
6.5±0.2
5.2±0.2
0.9
2.3 2.3
Unit: mm
0.6 MAX.
1.1±0.2
0.6 MAX
Maximum Ratings (Ta = 25°C)
Characteristic
Drain-source voltage
Drain-gate voltage (RGS = 20 kΩ)
Gate-source voltage
Drain current
DC (Note 1)
Pulse (Note 1)
Drain power dissipation (Tc = 25°C)
Single pulse avalanche energy
(Note 2)
Avalanche current
Repetitive avalanche energy (Note 3)
Channel temperature
Storage temperature range
Symbol
VDSS
VDGR
VGSS
ID
IDP
PD
EAS
IAR
EAR
Tch
Tstg
Rating
−200
−200
±20
−2.5
−10
20
97.5
−2.5
2.0
150
−55~150
Unit
V
V
V
A
W
mJ
A
mJ
°C
°C
123
0.8 MAX.
1.1 MAX.
0.6±0.15
0.6±0.15
JEDEC
―
JEITA
―
TOSHIBA
2-7J2B
Weight: 0.36 g (typ.)
Thermal Characteristics
Characteristic
Symbol
Max Unit
Thermal resistance, channel to case
Thermal resistance, channel to ambient
Rth (ch-c)
Rth (ch-a)
6.25
125
°C/W
°C/W
Note 1: Ensure that the channel temperature does not exceed 150°C.
Note 2: VDD = −50 V, Tch = 25°C (initial), L = −25.2 mH, IAR = −2.5 A RG = 25 Ω
Note 3: Repetitive rating: pulse width limited by maximum channel temperature
This transistor is an electrostatic-sensitive device. Handle with care.
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2SJ680
3
1
0.5
0.3
0.1
0.05
0.03
Duty = 0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.003
0.01
0.001
10 µ
100 µ
rth – tw
Single pulse
1m
10 m
100 m
Pulse width tw (S)
PDM
t
T
Duty = t/T
Rth (ch-c) = 6.25°C/W
1 10
100
Safe operating area
−30
ID max (pulse) *
−10
−5
−3
1 ms*
100 µs*
−1
−0.5
−0.3 DC
operation
−0.1
−0.05 * Single nonrepetitive pulse
−0.03 Tc = 25°C
Curves must be derated
−0.01 linearly with increase in
temperature.
−0.005
−0.1 −0.3
−1
−3
−10
VDSS max
−30 −100 −300
Drain-source voltage VDS (V)
EAS – Tch
100
80
60
40
20
0
25 50 75 100 125 150
Channel temperature Tch (°C)
15 V
−15 V
BVDSS
IAR
VDD
VDS
Test circuit
RG = 25 Ω
VDD = −50 V, L = 25.2 mH
Waveform
ΕAS
=
1
2
⋅L ⋅I2
⋅ ⎜⎜⎝⎛
BVDSS
BVDSS − VDD
⎟⎟⎠⎞
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5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet 2SJ680.PDF ] |
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