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4017 데이터시트 PDF




Fairchild에서 제조한 전자 부품 4017은 전자 산업 및 응용 분야에서
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부품번호 4017 기능
기능 Decade Counter/Divider
제조업체 Fairchild
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4017 데이터시트, 핀배열, 회로
October 1987
Revised January 2004
CD4017BC CD4022BC
Decade Counter/Divider with 10 Decoded Outputs
Divide-by-8 Counter/Divider with 8 Decoded Outputs
General Description
The CD4017BC is a 5-stage divide-by-10 Johnson counter
with 10 decoded outputs and a carry out bit.
The CD4022BC is a 4-stage divide-by-8 Johnson counter
with 8 decoded outputs and a carry-out bit.
These counters are cleared to their zero count by a logical
“1” on their reset line. These counters are advanced on the
positive edge of the clock signal when the clock enable sig-
nal is in the logical “0” state.
The configuration of the CD4017BC and CD4022BC per-
mits medium speed operation and assures a hazard free
counting sequence. The 10/8 decoded outputs are nor-
mally in the logical “0” state and go to the logical “1” state
only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry-out signal
completes a full cycle for every 10/8 clock input cycles and
is used as a ripple carry signal to any succeeding stages.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power Fan out of 2 driving 74L
TTL compatibility: or 1 driving 74LS
s Medium speed operation: 5.0 MHz (typ.)
with 10V VDD
s Low power: 10 µW (typ.)
s Fully static operation
Applications
• Automotive
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
Ordering Code:
Order Number Package Number
Package Description
CD4017BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4017BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4022BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4022BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Connection Diagrams
CD4017B
CD4022B
Top View
© 2004 Fairchild Semiconductor Corporation DS005950
Top View
www.fairchildsemi.com




4017 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics (Note 4)
TA= 25°C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time Carry Out Line
Carry Out Line
Decode Out Lines
tTLH, tTHL Transition Time Carry Out and Decode Out Lines
tTLH
tTHL
fCL Maximum Clock Frequency
tWL, tWH Minimum Clock Pulse Width
trCL, tfCL Clock Rise and Fall Time
tSU Minimum Clock Inhibit Data Setup Time
CIN Average Input Capacitance
Note 4: AC Parameters are guaranteed by DC correlated testing.
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CL = 15 pF
Measured with
Respect to Carry
Output Line
Min
1.0
2.5
3.0
Typ
Max
Units
415 800
160 320
130 250
240 480
85 170
70 140
500 1000
200 400
160 320
ns
ns
ns
200 360
100 180
ns
80 130
100 200
50 100 ns
40 80
2
5 MHz
6
125 250
45 90 ns
35 70
20
15 µs
5
120 240
40 80 ns
32 65
5 7.5 pF
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
RESET OPERATION
tPHL, tPLH
Propagation Delay Time
Carry Out Line
Carry Out Line
Decode Out Lines
tW
tREM
Minimum Reset
Pulse Width
Minimum Reset
Removal Time
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CL = 15 pF
Min Typ
Max
Units
415 800
160 320
130 250
240 480
85 170
70 140
500 1000
200 400
160 320
200 400
70 140
55 110
75 150
30 60
25 50
ns
ns
ns
ns
ns
www.fairchildsemi.com
4

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4017 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
7 www.fairchildsemi.com

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