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STK11C48 데이터시트 PDF




Simtek에서 제조한 전자 부품 STK11C48은 전자 산업 및 응용 분야에서
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PDF 형식의 STK11C48 자료 제공

부품번호 STK11C48 기능
기능 8K x 8 nvSRAM QuantumTrap CMOS Nonvolatile Static RAM
제조업체 Simtek
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STK11C48 데이터시트, 핀배열, 회로
STK11C48
2K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 25ns, 35ns and 45ns Access Times
STORE to Nonvolatile Elements Initiated by
Software
RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention in Nonvolatile Ele-
ments
• Commercial and Industrial Temperatures
• 28-Pin 300 mil PDIP, 300 mil SOIC and
350 mil SOIC Packages
DESCRIPTION
The Simtek STK11C48 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in the Nonvolatile Elements.
Data transfers from the SRAM to the Nonvolatile Ele-
ments (the STORE operation), or from Nonvolatile
Elements to SRAM (the RECALL operation), take
place using a software sequence. Transfers from the
Nonvolatile Elements to the SRAM (the RECALL
operation) also take place automatically on restora-
tion of power.
BLOCK DIAGRAM
Quantum Trap
32 x 512
A5 STORE
A6 STATIC RAM
A7
ARRAY
RECALL
A8 32 x 512
A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
G
E
W
A0 - A10
PIN CONFIGURATIONS
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 W
26 NC
25 A8
24 A9
23 NC
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
28 - 300 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
A0 - A10
W
Address Inputs
Write Enable
DQ0 - DQ7
E
Data In/Out
Chip Enable
G Output Enable
VCC Power (+ 5V)
VSS Ground
December 2002
1 Document Control # ML0003 rev 0.0




STK11C48 pdf, 반도체, 판매, 대치품
STK11C48
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1 #2 Alt.
PARAMETER
12 tAVAV
13 tWLWH
14 tELWH
15 tDVWH
16 tWHDX
17 tAVWH
18 tAVWL
19 tWHAX
20 tWLQZh, i
21 tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
tWP Write Pulse Width
tCW Chip Enable to End of Write
tDW Data Set-up to End of Write
tDH Data Hold after End of Write
tAW Address Set-up to End of Write
tAS Address Set-up to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
ADDRESS
12
tAVAV
14
tELWH
E
(VCC = 5.0V + 10%)
STK11C48-25
MIN MAX
STK11C48-35
MIN MAX
STK11C48-45
MIN MAX
UNITS
25 35 45 ns
20 25 30 ns
20 25 30 ns
10 12 15 ns
0 0 0 ns
20 25 30 ns
0 0 0 ns
0 0 0 ns
10 13 15 ns
5 5 5 ns
19
tWHAX
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledj
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
19
tEHAX
W
DATA IN
DATA OUT
December 2002
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
4 Document Control # ML0003 rev 0.0

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STK11C48 전자부품, 판매, 대치품
STK11C48
DEVICE OPERATION
The STK11C48 is a versatile memory chip that pro-
vides several modes of operation. The STK11C48
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 Nonvolatile Elements shadow to which the
SRAM information can be copied or from which the
SRAM can be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C48 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between Vcc
and Vss, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK11C48 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-10 determines which of the 2,048 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
SOFTWARE NONVOLATILE STORE
The STK11C48 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
000 (hex)
555 (hex)
2AA (hex)
7FF (hex)
0F0 (hex)
70F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
000 (hex)
555 (hex)
2AA (hex)
7FF (hex)
0F0 (hex)
70E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
December 2002
7 Document Control # ML0003 rev 0.0

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관련 데이터시트

부품번호상세설명 및 기능제조사
STK11C48

8K x 8 nvSRAM QuantumTrap CMOS Nonvolatile Static RAM

Simtek
Simtek

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